Conferences in DBLP
Fred J. Pollack New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Rotenberg , James E. Smith Control Independence in Trace Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Glenn Reinman , Brad Calder , Todd M. Austin Fetch Directed Instruction Prefetching. [Citation Graph (0, 0)][DBLP ] Conf ] Timothy H. Heil , Zak Smith , James E. Smith Improving Branch Predictors by Correlating on Data Values. [Citation Graph (0, 0)][DBLP ] Conf ] Artur Klauser , Dirk Grunwald Instruction Fetch Mechanisms for Multipath Execution Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew Wolfe , Derek B. Noonburg A Superscalar 3D Graphics Engine. [Citation Graph (0, 0)][DBLP ] Conf ] Tulika Mitra , Tzi-cker Chiueh Dynamic 3D Graphics Workload Characterization and the Architectural Implications. [Citation Graph (0, 0)][DBLP ] Conf ] Jesús Corbal , Roger Espasa , Mateo Valero Exploiting a New Level of DLP in Multimedia Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Sergei Y. Larin , Thomas M. Conte Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Charles Lefurgy , Eva Piccininni , Trevor N. Mudge Evaluation of a High Performance Code Compression Method. [Citation Graph (0, 0)][DBLP ] Conf ] Lea Hwang Lee , Jeff Scott , Bill Moyer , John Arends Low-Cost Branch Folding for Embedded Applications with Small Tight Loops. [Citation Graph (0, 0)][DBLP ] Conf ] Santosh G. Abraham , Scott A. Mahlke Automatic and Efficient Evaluation of Memory Hierarchies for Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jamison D. Collins , Dean M. Tullsen Hardware Identification of Cache Conflict Misses. [Citation Graph (0, 0)][DBLP ] Conf ] Sangyeun Cho , Pen-Chung Yew , Gyungho Lee Access Region Locality for High-Bandwidth Processor Memory System Design. [Citation Graph (0, 0)][DBLP ] Conf ] Vijay S. Pai , Sarita V. Adve Code Transformations to Improve Memory Parallelism. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel A. Connors , Wen-mei W. Hwu Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results. [Citation Graph (0, 0)][DBLP ] Conf ] Soner Önder , Rajiv Gupta Dynamic Memory Disambiguation in the Presence of Out-of-Order Store Issuing. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Moshovos , Gurindar S. Sohi Read-After-Read Memory Dependence Prediction. [Citation Graph (0, 0)][DBLP ] Conf ] Teresa Monreal , Antonio González , Mateo Valero , José González , Víctor Viñals Delaying Physical Register Allocation through Virtual-Physical Registers. [Citation Graph (0, 0)][DBLP ] Conf ] Bruce Shriver Core Technologies in Hardware and Software. [Citation Graph (0, 0)][DBLP ] Conf ] Todd M. Austin DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Oskin , Justin Hensley , Diana Keen , Frederic T. Chong , Matthew K. Farrens , Aneet Chopra Exploiting ILP in Page-based Intelligent Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Craig B. Zilles , Joel S. Emer , Gurindar S. Sohi The Use of Multithreading for Exception Handling. [Citation Graph (0, 0)][DBLP ] Conf ] Pedro Marcuello , Jordi Tubella , Antonio González Value Prediction for Speculative Multithreaded Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Enric Musoll Predicting the Usefulness of a Block Result: A Micro-Architectural Technique for High-Performance Low-Power Processors. [Citation Graph (0, 0)][DBLP ] Conf ] David H. Albonesi Selective Cache Ways: On-Demand Cache Resource Allocation. [Citation Graph (0, 0)][DBLP ] Conf ] Jay Bharadwaj , Kishore N. Menezes , Chris McKinsey Wavefront Scheduling: Path based Data Representation and Scheduling of Subgraphs. [Citation Graph (0, 0)][DBLP ] Conf ] Alexandre E. Eichenberger , Waleed Meleis Balance Scheduling: Weighting Branch Tradeoffs in Superblocks. [Citation Graph (0, 0)][DBLP ] Conf ] Kemal Ebcioglu , Erik R. Altman , Sumedh W. Sathaye , Michael Gschwind Optimizations and Oracle Parallelism with Dynamic Translation. [Citation Graph (0, 0)][DBLP ] Conf ] 