Conferences in DBLP
Michael Butler , Yale N. Patt An investigation of the performance of various dynamic scheduling techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Kevin B. Theobald , Guang R. Gao , Laurie J. Hendren On the limits of program parallelism and its smoothability. [Citation Graph (0, 0)][DBLP ] Conf ] Sriram Vajapeyam , Wei-Chung Hsu On the instruction-level characteristics of scalar code in highly-vectorized scientific applications. [Citation Graph (0, 0)][DBLP ] Conf ] Meng-chou Chang , Feipei Lai , Rung-Ji Shang Exploiting instruction-level parallelism with the conjugate register file scheme. [Citation Graph (0, 0)][DBLP ] Conf ] Thang Tran , Chuan-lin Wu Limitation of superscalar microprocessor performance. [Citation Graph (0, 0)][DBLP ] Conf ] Chien-Ming Chen , Yunn Yen Chen , Chung-Ta King Branch merging for effective exploitation of instruction-level parallelism. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandro De Gloria , Paolo Faraboschi , Mauro Olivieri A non-deterministic scheduler for a software pipelining compiler. [Citation Graph (0, 0)][DBLP ] Conf ] Scott A. Mahlke , David C. Lin , William Y. Chen , Richard E. Hank , Roger A. Bringmann Effective compiler support for predicated execution using the hyperblock. [Citation Graph (0, 0)][DBLP ] Conf ] Soo-Mook Moon , Kemal Ebcioglu An efficient resource-constrained global scheduling technique for superscalar and VLIW processors. [Citation Graph (0, 0)][DBLP ] Conf ] V. H. Allen , J. Janardhan , R. M. Lee , M. Srinivas Enhanced region scheduling on a program dependence graph. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew Wolfe , Alex Chanin Executing compressed programs on an embedded RISC architecture. [Citation Graph (0, 0)][DBLP ] Conf ] William Y. Chen , Roger A. Bringmann , Scott A. Mahlke , Richard E. Hank , James E. Sicolo An efficient architecture for loop based data preloading. [Citation Graph (0, 0)][DBLP ] Conf ] John W. C. Fu , Janak H. Patel , Bob L. Janssens Stride directed prefetching in scalar processors. [Citation Graph (0, 0)][DBLP ] Conf ] André Seznec , Karl Courtel Controlling and sequencing a heavily pipelined floating-point operator. [Citation Graph (0, 0)][DBLP ] Conf ] Augustus K. Uht , Darin B. Johnson Data path issues in a highly concurrent machine. [Citation Graph (0, 0)][DBLP ] Conf ] Bogong Su , Wei Zhao , Zhizhong Tang , Stanley Habib A VLIW architecture for optimal execution of branch-intensive loops. [Citation Graph (0, 0)][DBLP ] Conf ] Michael J. Knieser , Christos A. Papachristou Y-Pipe: a conditional branching scheme without pipeline delays. [Citation Graph (0, 0)][DBLP ] Conf ] Tse-Yu Yeh , Yale N. Patt A comprehensive instruction fetch mechanism for a processor supporting speculative execution. [Citation Graph (0, 0)][DBLP ] Conf ] Carl J. Beckmann , Constantine D. Polychronopoulos Microarchitecture support for dynamic scheduling of acyclic task graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Nadeem Malik , Richard J. Eickemeyer , Stamatis Vassiliadis Interlock collapsing ALU for increased instruction-level parallelism. [Citation Graph (0, 0)][DBLP ] Conf ] B. Ramakrishna Rau , Michael S. Schlansker , Parthasarathy P. Tirumalai Code generation schema for modulo scheduled loops. [Citation Graph (0, 0)][DBLP ] Conf ] Nancy J. Warter , Grant E. Haab , Krishna Subramanian , John W. Bockhaus Enhanced modulo scheduling for loops with conditional branches. [Citation Graph (0, 0)][DBLP ] Conf ] Steven R. Vegdahl A dynamic-programming technique for compacting loops. [Citation Graph (0, 0)][DBLP ] Conf ] Philip Lenir , Ramaswamy Govindarajan , Shashank S. Nemawarkar Exploiting instruction-level parallelism: the multithreaded approach. [Citation Graph (0, 0)][DBLP ] Conf ] Gary S. Tyson , Matthew K. Farrens , Andrew R. Pleszkun MISC: a Multiple Instruction Stream Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Tokuzo Kiyohara , John C. Gyllenhaal Code scheduling for VLIW/superscalar processors with limited register files. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas M. Conte Tradeoffs in processor/memory interfaces for superscalar processors. [Citation Graph (0, 0)][DBLP ] Conf ] Brian K. Bray , Michael J. Flynn Translation hint buffers to reduce access time of physically-addressed instruction caches. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew K. Farrens , Arvin Park , Gary S. Tyson Modifying VM hardware to reduce address pin requirements. [Citation Graph (0, 0)][DBLP ] Conf ] Kent D. Wilken , David W. Goodwin Toward zero-cost branches using instruction registers. [Citation Graph (0, 0)][DBLP ] Conf ] Youfeng Wu Ordering functions for improving memory reference locality in a shared memory multiprocessor system. [Citation Graph (0, 0)][DBLP ] Conf ] William L. Lynch , Brian K. Bray , Michael J. Flynn The effect of page allocation on caches. [Citation Graph (0, 0)][DBLP ] Conf ] David Bernstein , Doron Cohen , Yuval Lavon , Vladimir Rainish Performance evaluation of instruction scheduling on the IBM RISC System/6000. [Citation Graph (0, 0)][DBLP ] Conf ] Manoj Franklin , Gurindar S. Sohi Register traffic analysis for streamlining inter-operation communication in fine-grain parallel processors. [Citation Graph (0, 0)][DBLP ] Conf ] Takaaki Kato , Toshihisa Ono , Nader Bagherzadeh Performance analysis and design methodology for a scalable superscalar architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Steven J. Beaty Lookahead scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Philip H. Sweany , Steven J. Beaty Dominator-path scheduling: a global scheduling method. [Citation Graph (0, 0)][DBLP ] Conf ] Brian A. Malloy , Rajiv Gupta , Mary Lou Soffa A shape matching approach for scheduling fine-grained parallelism. [Citation Graph (0, 0)][DBLP ] Conf ] Shih-Hsu Huang , Cheng-Tsung Hwang , Yu-Chin Hsu , Yen-Jen Oyang A new approach to schedule operations across nested-ifs and nested-loops. [Citation Graph (0, 0)][DBLP ] Conf ] Harry Dwyer , Hwa C. Torng An out-of-order superscalar processor with speculative execution and fast, precise interrupts. [Citation Graph (0, 0)][DBLP ] Conf ] Benoît Dupont de Dinechin StaCS: a Static Control Superscalar architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Andrea Capitanio , Nikil D. Dutt , Alexandru Nicolau Partitioned register files for VLIWs: a preliminary analysis of tradeoffs. [Citation Graph (0, 0)][DBLP ] Conf ] 