Conferences in DBLP
M. Rajagopalan , Vicki H. Allan Efficient scheduling of fine grain parallelism in loops. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Müller Employing finite automata for resource scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Zhizhong Tang , Gang Chen , Chihong Zhang , Yingwei Zhang , Bogong Su , Stanley Habib GPMB - software pipelining branch-intensive loops. [Citation Graph (0, 0)][DBLP ] Conf ] Tim Stanley , Michael Upton , Patrick Sherhart , Trevor N. Mudge , Richard B. Brown A microarchitectural performance evaluation of a 3.2 Gbyte/s microprocessor bus. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew Wolfe , Rodney Boleyn Two-ported cache alternatives for superscalar processors. [Citation Graph (0, 0)][DBLP ] Conf ] Soo-Mook Moon , Kemal Ebcioglu A study on the number of memory ports in multiple instruction issue machines. [Citation Graph (0, 0)][DBLP ] Conf ] Barton Sano , Alvin M. Despain The 16-fold way: a microparallel taxonomy. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Butler , Yale N. Patt A comparative performance evaluation of various state maintenance mechanisms. [Citation Graph (0, 0)][DBLP ] Conf ] B. Ramakrishna Rau Dynamically scheduled VLIW processors. [Citation Graph (0, 0)][DBLP ] Conf ] Apoorv Srivastava , Alvin M. Despain Prophetic branches: a branch architecture for code compaction and efficient execution. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew K. Farrens , Pius Ng , Phil Nico A comparision of superscalar and decoupled access/execute architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Lawrence Rauchwerger , Pradeep K. Dubey , Ravi Nair Measuring limits of parallelism and characterizing its vulnerability to resource constraints. [Citation Graph (0, 0)][DBLP ] Conf ] A. P. Wim Böhm , Walid A. Najjar , Bhanu Shankar , Lucas Roh An evaluation of bottom-up and top-down thread generation techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Gary S. Tyson , Matthew K. Farrens Techniques for extracting instruction level parallelism on MIMD architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Santosh G. Abraham , Rabin A. Sugumar , Daniel Windheiser , B. Ramakrishna Rau , Rajiv Gupta Predictability of load/store instruction latencies. [Citation Graph (0, 0)][DBLP ] Conf ] Dionisios N. Pnevmatikatos , Manoj Franklin , Gurindar S. Sohi Control flow prediction for dynamic ILP processors. [Citation Graph (0, 0)][DBLP ] Conf ] Tse-Yu Yeh , Yale N. Patt Branch history table indexing to prevent pipeline bubbles in wide-issue superscalar processors. [Citation Graph (0, 0)][DBLP ] Conf ] Mark A. Franklin , Tienyo Pan Clocked and asynchronous instruction pipelines. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandra Costa , Alessandro De Gloria , Paolo Faraboschi , Mauro Olivieri An analysis of dynamic scheduling techniques for symbolic applications. [Citation Graph (0, 0)][DBLP ] Conf ] Nathalie Drach , André Seznec MIDEE: smoothing branch and instruction cache miss penalties on deep pipelines. [Citation Graph (0, 0)][DBLP ] Conf ] Mayan Moudgill , Keshav Pingali , Stamatis Vassiliadis Register renaming and dynamic speculation: an alternative approach. [Citation Graph (0, 0)][DBLP ] Conf ] Roger A. Bringmann , Scott A. Mahlke , Richard E. Hank , John C. Gyllenhaal , Wen-mei W. Hwu Speculative execution exception recovery using write-back suppression. [Citation Graph (0, 0)][DBLP ] Conf ] Trung A. Diep , John Paul Shen , Mike Phillip EXPLORER: a retargetable and visualization-based trace-driven simulator for superscalar processors. [Citation Graph (0, 0)][DBLP ] Conf ] Ing-Jer Huang , Alvin M. Despain An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processors. [Citation Graph (0, 0)][DBLP ] Conf ] Richard E. Hank , Scott A. Mahlke , Roger A. Bringmann , John C. Gyllenhaal , Wen-mei W. Hwu Superblock formation using static program analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Smotherman , Shuchi Chawla II , Stan Cox , Brian A. Malloy Instruction scheduling for the Motorola 88110. [Citation Graph (0, 0)][DBLP ] Conf ] H. Fatih Ugurdag , Christos A. Papachristou A VLIW architecture based on shifting register files. [Citation Graph (0, 0)][DBLP ] Conf ] 