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Conferences in DBLP

International Symposium on Microarchitecture (MICRO) (micro)
2001 (conf/micro/2001)

  1. Harvey G. Cragon, Ernest Cockrell Jr.
    Fifty years of microarchitecture. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:2- [Conf]
  2. Chen-Yong Cher, T. N. Vijaykumar
    Skipper: a microarchitecture for exploiting control-flow independence. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:4-15 [Conf]
  3. Brian Fahs, Satarupa Bose, Matthew M. Crum, Brian Slechta, Francesco Spadini, Tony Tung, Sanjay J. Patel, Steven S. Lumetta
    Performance characterization of a hardware mechanism for dynamic optimization. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:16-27 [Conf]
  4. Eric Rotenberg
    Using variable-MHz microprocessors to efficiently handle uncertainty in real-time systems. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:28-39 [Conf]
  5. Ramadass Nagarajan, Karthikeyan Sankaralingam, Doug Burger, Stephen W. Keckler
    A design space evaluation of grid processor architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:40-51 [Conf]
  6. Michael D. Powell, Amit Agarwal, T. N. Vijaykumar, Babak Falsafi, Kaushik Roy
    Reducing set-associative cache energy via way-prediction and selective direct-mapping. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:54-65 [Conf]
  7. Yuan Xie, Wayne Wolf, Haris Lekatsas
    A code decompression architecture for VLIW processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:66-75 [Conf]
  8. Byung-Kwon Chung, Jinsuo Zhang, Jih-Kwon Peir, Shih-Chang Lai, Konrad Lai
    Direct load: dependence-linked dataflow resolution of load address and cache coordinate. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:76-87 [Conf]
  9. Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose
    Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:90-101 [Conf]
  10. Wei Zhang 0002, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, David Duarte, Yuh-Fang Tsai
    Exploiting VLIW schedule slacks for dynamic and leakage energy reduction. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:102-113 [Conf]
  11. John S. Seng, Eric Tune, Dean M. Tullsen
    Reducing power with dynamic critical path information. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:114-123 [Conf]
  12. Emmett Witchel, Samuel Larsen, C. Scott Ananian, Krste Asanovic
    Direct addressed caches for reduced power consumption. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:124-133 [Conf]
  13. Andrew Wolfe
    Emerging applications for the connected home. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:136- [Conf]
  14. Matthew C. Merten, Wen-mei W. Hwu
    Modulo schedule buffers. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:138-149 [Conf]
  15. Alex Aletà, Josep M. Codina, F. Jesús Sánchez, Antonio González
    Graph-partitioning based instruction scheduling for clustered processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:150-159 [Conf]
  16. Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
    Modulo scheduling with integrated register spilling for clustered VLIW architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:160-169 [Conf]
  17. Artour Stoutchinin, François de Ferrière
    Efficient static single assignment form for predication. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:172-181 [Conf]
  18. Youngsoo Choi, Allan D. Knies, Luke Gerke, Tin-Fook Ngai
    The impact of if-conversion and branch prediction on program execution on the Intel Itanium processor. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:182-191 [Conf]
  19. Gary William Grewal, Thomas Charles Wilson
    Mapping reference code to irregular DSPs within the retargetable, optimizing compiler COGEN(T). [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:192-202 [Conf]
  20. Mary D. Brown, Jared Stark, Yale N. Patt
    Select-free instruction scheduling logic. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:204-213 [Conf]
  21. Joydeep Ray, James C. Hoe, Babak Falsafi
    Dual use of superscalar datapath for transient-fault detection and recovery. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:214-224 [Conf]
  22. Masahiro Goshima, Kengo Nishino, Toshiaki Kitamura, Yasuhiko Nakashima, Shinji Tomita, Shin-ichiro Mori
    A high-speed dynamic instruction scheduling scheme for superscalar processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:225-236 [Conf]
  23. Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
    Reducing the complexity of the register file in dynamic superscalar processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:237-248 [Conf]
  24. Christopher J. Hughes, Jayanth Srinivasan, Sarita V. Adve
    Saving energy with architectural and frequency adaptations for multimedia applications. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:250-261 [Conf]
  25. John W. Sias, Hillery C. Hunter, Wen-mei W. Hwu
    Enhancing loop buffering of media and telecommunications applications using low-overhead predication. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:262-273 [Conf]
  26. Osman S. Unsal, Raksit Ashok, Israel Koren, C. Mani Krishna, Csaba Andras Moritz
    Cool-cache for hot multimedia. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:274-283 [Conf]
  27. Emile Hsieh, Vladimir Pentkovski, Thomas Piazza
    ZR: a 3D API transparent technology for chunk rendering. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:284-291 [Conf]
  28. Ravi Rajwar, James R. Goodman
    Speculative lock elision: enabling highly concurrent multithreaded execution. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:294-305 [Conf]
  29. Jamison D. Collins, Dean M. Tullsen, Hong Wang, John Paul Shen
    Dynamic speculative precomputation. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:306-317 [Conf]
  30. Dean M. Tullsen, Jeffery A. Brown
    Handling long-latency loads in a simultaneous multithreading processor. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:318-327 [Conf]
  31. Milo M. K. Martin, Daniel J. Sorin, Harold W. Cain, Mark D. Hill, Mikko H. Lipasti
    Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:328-337 [Conf]
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002