Conferences in DBLP
Harvey G. Cragon , Ernest Cockrell Jr. Fifty years of microarchitecture. [Citation Graph (0, 0)][DBLP ] Conf ] Chen-Yong Cher , T. N. Vijaykumar Skipper: a microarchitecture for exploiting control-flow independence. [Citation Graph (0, 0)][DBLP ] Conf ] Brian Fahs , Satarupa Bose , Matthew M. Crum , Brian Slechta , Francesco Spadini , Tony Tung , Sanjay J. Patel , Steven S. Lumetta Performance characterization of a hardware mechanism for dynamic optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Rotenberg Using variable-MHz microprocessors to efficiently handle uncertainty in real-time systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ramadass Nagarajan , Karthikeyan Sankaralingam , Doug Burger , Stephen W. Keckler A design space evaluation of grid processor architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Michael D. Powell , Amit Agarwal , T. N. Vijaykumar , Babak Falsafi , Kaushik Roy Reducing set-associative cache energy via way-prediction and selective direct-mapping. [Citation Graph (0, 0)][DBLP ] Conf ] Yuan Xie , Wayne Wolf , Haris Lekatsas A code decompression architecture for VLIW processors. [Citation Graph (0, 0)][DBLP ] Conf ] Byung-Kwon Chung , Jinsuo Zhang , Jih-Kwon Peir , Shih-Chang Lai , Konrad Lai Direct load: dependence-linked dataflow resolution of load address and cache coordinate. [Citation Graph (0, 0)][DBLP ] Conf ] Dmitry Ponomarev , Gurhan Kucuk , Kanad Ghose Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Zhang 0002 , Narayanan Vijaykrishnan , Mahmut T. Kandemir , Mary Jane Irwin , David Duarte , Yuh-Fang Tsai Exploiting VLIW schedule slacks for dynamic and leakage energy reduction. [Citation Graph (0, 0)][DBLP ] Conf ] John S. Seng , Eric Tune , Dean M. Tullsen Reducing power with dynamic critical path information. [Citation Graph (0, 0)][DBLP ] Conf ] Emmett Witchel , Samuel Larsen , C. Scott Ananian , Krste Asanovic Direct addressed caches for reduced power consumption. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew Wolfe Emerging applications for the connected home. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew C. Merten , Wen-mei W. Hwu Modulo schedule buffers. [Citation Graph (0, 0)][DBLP ] Conf ] Alex Aletà , Josep M. Codina , F. Jesús Sánchez , Antonio González Graph-partitioning based instruction scheduling for clustered processors. [Citation Graph (0, 0)][DBLP ] Conf ] Javier Zalamea , Josep Llosa , Eduard Ayguadé , Mateo Valero Modulo scheduling with integrated register spilling for clustered VLIW architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Artour Stoutchinin , François de Ferrière Efficient static single assignment form for predication. [Citation Graph (0, 0)][DBLP ] Conf ] Youngsoo Choi , Allan D. Knies , Luke Gerke , Tin-Fook Ngai The impact of if-conversion and branch prediction on program execution on the Intel Itanium processor. [Citation Graph (0, 0)][DBLP ] Conf ] Gary William Grewal , Thomas Charles Wilson Mapping reference code to irregular DSPs within the retargetable, optimizing compiler COGEN(T). [Citation Graph (0, 0)][DBLP ] Conf ] Mary D. Brown , Jared Stark , Yale N. Patt Select-free instruction scheduling logic. [Citation Graph (0, 0)][DBLP ] Conf ] Joydeep Ray , James C. Hoe , Babak Falsafi Dual use of superscalar datapath for transient-fault detection and recovery. [Citation Graph (0, 0)][DBLP ] Conf ] Masahiro Goshima , Kengo Nishino , Toshiaki Kitamura , Yasuhiko Nakashima , Shinji Tomita , Shin-ichiro Mori A high-speed dynamic instruction scheduling scheme for superscalar processors. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev Balasubramonian , Sandhya Dwarkadas , David H. Albonesi Reducing the complexity of the register file in dynamic superscalar processors. [Citation Graph (0, 0)][DBLP ] Conf ] Christopher J. Hughes , Jayanth Srinivasan , Sarita V. Adve Saving energy with architectural and frequency adaptations for multimedia applications. [Citation Graph (0, 0)][DBLP ] Conf ] John W. Sias , Hillery C. Hunter , Wen-mei W. Hwu Enhancing loop buffering of media and telecommunications applications using low-overhead predication. [Citation Graph (0, 0)][DBLP ] Conf ] Osman S. Unsal , Raksit Ashok , Israel Koren , C. Mani Krishna , Csaba Andras Moritz Cool-cache for hot multimedia. [Citation Graph (0, 0)][DBLP ] Conf ] Emile Hsieh , Vladimir Pentkovski , Thomas Piazza ZR: a 3D API transparent technology for chunk rendering. [Citation Graph (0, 0)][DBLP ] Conf ] Ravi Rajwar , James R. Goodman Speculative lock elision: enabling highly concurrent multithreaded execution. [Citation Graph (0, 0)][DBLP ] Conf ] Jamison D. Collins , Dean M. Tullsen , Hong Wang , John Paul Shen Dynamic speculative precomputation. [Citation Graph (0, 0)][DBLP ] Conf ] Dean M. Tullsen , Jeffery A. Brown Handling long-latency loads in a simultaneous multithreading processor. [Citation Graph (0, 0)][DBLP ] Conf ] Milo M. K. Martin , Daniel J. Sorin , Harold W. Cain , Mark D. Hill , Mikko H. Lipasti Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing. [Citation Graph (0, 0)][DBLP ] Conf ] 