Conferences in DBLP

International Symposium on Microarchitecture (MICRO) (micro)
1994 (conf/micro/1994)

1. Youfeng Wu, James R. Larus
   Static branch frequency and program profile analysis. [Citation Graph (0, 0)][DBLP]
   MICRO, 1994, pp:1-11 [Conf]
   
2. Thomas M. Conte, Burzin A. Patel, J. Stan Cox
   Using branch handling hardware to support profile-driven optimization. [Citation Graph (0, 0)][DBLP]
   MICRO, 1994, pp:12-21 [Conf]
   
3. Po-Yung Chang, Eric Hao, Tse-Yu Yeh, Yale N. Patt
   Branch classification: a new mechanism for improving branch predictor performance. [Citation Graph (0, 0)][DBLP]
   MICRO, 1994, pp:22-31 [Conf]
   
4. Andrew R. Pleszkun
   Techniques for compressing program address traces. [Citation Graph (0, 0)][DBLP]
   MICRO, 1994, pp:32-39 [Conf]
   
5. Michael S. Schlansker, Vinod Kathail, Sadun Anik
   Height reduction of control recurrences for ILP processors. [Citation Graph (0, 0)][DBLP]
   MICRO, 1994, pp:40-51 [Conf]
   
6. Derek B. Noonburg, John Paul Shen
   Theoretical modeling of superscalar processor performance. [Citation Graph (0, 0)][DBLP]
   MICRO, 1994, pp:52-62 [Conf]
   
7. B. Ramakrishna Rau
   Iterative modulo scheduling: an algorithm for software pipelining loops. [Citation Graph (0, 0)][DBLP]
   MICRO, 1994, pp:63-74 [Conf]
   
8. Alexandre E. Eichenberger, Edward S. Davidson, Santosh G. Abraham
   Minimum register requirements for a modulo schedule. [Citation Graph (0, 0)][DBLP]
   MICRO, 1994, pp:75-84 [Conf]
   
9. Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao
   Minimizing register requirements under resource-constrained rate-optimal software pipelining. [Citation Graph (0, 0)][DBLP]
   MICRO, 1994, pp:85-94 [Conf]
   
10. Jian Wang, Andreas Krall, M. Anton Ertl, Christine Eisenbeis
    Software pipelining with register allocation and spilling. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:95-99 [Conf]
    
11. Peter Dahl, Matthew T. O'Keefe
    Reducing memory traffic with CRegs. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:100-104 [Conf]
    
12. David Bernstein, Doron Cohen, Dror E. Maydan
    Dynamic memory disambiguation for array references. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:105-111 [Conf]
    
13. Bogong Su, Stanley Habib, Wei Zhao, Jian Wang, Youfeng Wu
    A study of pointer aliasing for software pipelining using run-time disambiguation. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:112-117 [Conf]
    
14. Yoji Yamada, John Gyllenhall, Grant Haab, Wen-mei W. Hwu
    Data relocation and prefetching for programs with large data sets. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:118-127 [Conf]
    
15. Lishing Liu
    Cache designs with partial address matching. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:128-136 [Conf]
    
16. Ching-Long Su, Alvin M. Despain
    Minimizing branch misprediction penalties for superpipelined processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:138-142 [Conf]
    
17. Eric Sprangle, Yale N. Patt
    Facilitating superscalar processing via a combined static/dynamic register renaming scheme. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:143-147 [Conf]
    
18. Raymond Lo, Sun Chan, Fred C. Chow, Shin-Ming Liu
    Improving resource utilization of the MIPS R8000 via post-scheduling global instruction distribution. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:148-152 [Conf]
    
19. Michael Golden, Trevor N. Mudge
    A comparison of two pipeline organizations. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:153-161 [Conf]
    
20. Manoj Franklin, Mark Smotherman
    A fill-unit approach to multiple instruction issue. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:162-171 [Conf]
    
21. Rahul Razdan, Michael D. Smith
    A high-performance microarchitecture with hardware-programmable functional units. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:172-180 [Conf]
    
22. Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi
    The anatomy of the register file in a multiscalar processor. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:181-190 [Conf]
    
23. Jan Hoogerbrugge, Henk Corporaal
    Register file port requirements of transport triggered architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:191-195 [Conf]
    
24. Gary S. Tyson
    The effects of predicated execution on branch prediction. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:196-206 [Conf]
    
25. Jonathan P. Vogel, Bruce K. Holmer
    Analysis of the conditional skip instructions of the HP precision architecture. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:207-216 [Conf]
    
26. Scott A. Mahlke, Richard E. Hank, Roger A. Bringmann, John C. Gyllenhaal, David M. Gallagher, Wen-mei W. Hwu
    Characterizing the impact of predicated execution on branch prediction. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:217-227 [Conf]
    
27. Eric Hao, Po-Yung Chang, Yale N. Patt
    The effect of speculatively updating branch history on branch prediction accuracy, revisited. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:228-232 [Conf]