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Conferences in DBLP
- Nicholas C. Gloy, Michael D. Smith, Cliff Young
Performance issues in correlated branch prediction schemes. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:3-14 [Conf]
- Ravi Nair
Dynamic path-based branch correlation. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:15-23 [Conf]
- Brad Calder, Dirk Grunwald, Amitabh Srivastava
The predictability of branches in libraries. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:24-34 [Conf]
- Pritpal S. Ahuja, Douglas W. Clark, Anne Rogers
The performance impact of incomplete bypassing in processor pipelines. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:36-45 [Conf]
- Vasanth Bala, Norman Rubin
Efficient instruction scheduling using finite state automata. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:46-56 [Conf]
- Michael S. Schlansker, Vinod Kathail
Critical path reduction for scalar programs. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:57-69 [Conf]
- Andrew S. Huang, John Paul Shen
A limit study of local memory requirements using value reuse profiles. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:71-81 [Conf]
- Todd M. Austin, Gurindar S. Sohi
Zero-cycle loads: microarchitecture support for reducing load latency. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:82-92 [Conf]
- Gary S. Tyson, Matthew K. Farrens, John Matthews, Andrew R. Pleszkun
A modified approach to data cache management. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:93-103 [Conf]
- Vicki H. Allan, U. R. Shah, K. M. Reddy
Petri net versus modulo scheduling for software pipelining. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:105-110 [Conf]
- Nancy J. Warter-Perez, Noubar Partamian
Modulo scheduling with multiple initiation intervals. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:111-119 [Conf]
- B. Natarajan, Michael S. Schlansker
Spill-free parallel scheduling of basic blocks. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:119-124 [Conf]
- Jack W. Davidson, Sanjay Jinturkar
Improving instruction-level parallelism by loop unrolling and dynamic memory disambiguation. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:125-132 [Conf]
- John R. Gurd, David F. Snelling
Self-regulation of workload in the Manchester Data-Flow computer. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:135-145 [Conf]
- Marco Fillo, Stephen W. Keckler, William J. Dally, Nicholas P. Carter, Andrew Chang, Yevgeny Gurevich, Whay Sing Lee
The M-Machine multicomputer. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:146-156 [Conf]
- Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau
Region-based compilation: an introduction and motivation. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:158-168 [Conf]
- Cindy Norris, Lori L. Pollock
An experimental study of several cooperative register allocation and instruction scheduling strategies. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:169-179 [Conf]
- Alexandre E. Eichenberger, Edward S. Davidson
Register allocation for predicated code. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:180-191 [Conf]
- Barry S. Fagin, Kathryn Russell
Partial resolution in branch target buffers. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:193-198 [Conf]
- Brad Calder, Dirk Grunwald, Joel S. Emer
A system level perspective on branch architecture performance. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:199-206 [Conf]
- Thomas M. Conte, Sumedh W. Sathaye
Dynamic rescheduling: a technique for object code compatibility in VLIW architectures. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:208-218 [Conf]
- Mark Smotherman, Manoj Franklin
Improving CISC instruction decoding performance using a fill unit. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:219-229 [Conf]
- Mikko H. Lipasti, William J. Schmidt, Steven R. Kunkel, Robert R. Roediger
SPAID: software prefetching in pointer- and call-intensive environments. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:231-236 [Conf]
- Tien-Fu Chen
An effective programmable prefetch engine for on-chip caches. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:237-242 [Conf]
- Toshihiro Ozawa, Yasunori Kimura, Shin'ichiro Nishizaki
Cache miss heuristics and preloading techniques for general-purpose programs. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:243-248 [Conf]
- Po-Ying Chang, Eric Hao, Yale N. Patt
Alternative implementations of hybrid branch predictors. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:252-257 [Conf]
- Simonjit Dutta, Manoj Franklin
Control flow prediction with tree-like subgraphs for superscalar processors. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:258-263 [Conf]
- Stuart Sechrest, Chih-Chieh Lee, Trevor N. Mudge
The role of adaptivity in two-level adaptive branch prediction. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:264-269 [Conf]
- Lucas Roh, Walid A. Najjar
Design of storage hierarchy in multithreaded architectures. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:271-278 [Conf]
- Stéphan Jourdan, Pascal Sainrat, Daniel Litaize
An investigation of the performance of various instruction-issue buffer topologies. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:279-284 [Conf]
- Subbarao Palacharla, James E. Smith
Decoupling integer execution in superscalar processors. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:285-290 [Conf]
- Luis A. Lozano, Guang R. Gao
Exploiting short-lived variables in superscalar processors. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:292-302 [Conf]
- Johan Janssen, Henk Corporaal
Partitioned register file for TTAs. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:303-312 [Conf]
- Augustus K. Uht, Vijay Sindagi, Kelley Hall
Disjoint eager execution: an optimal form of speculative execution. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:313-325 [Conf]
- Daniel M. Lavery, Wen-mei W. Hwu
Unrolling-based optimizations for modulo scheduling. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:327-337 [Conf]
- Alexandre E. Eichenberger, Edward S. Davidson
Stage scheduling: a technique to reduce the register requirements of a modulo schedule. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:338-349 [Conf]
- Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González
Hypernode reduction modulo scheduling. [Citation Graph (0, 0)][DBLP]
MICRO, 1995, pp:350-360 [Conf]
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