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Conferences in DBLP

International Symposium on Microarchitecture (MICRO) (micro)
2005 (conf/micro/2005)


  1. Message from the General Chairs. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:- [Conf]

  2. Message from the Program Co-Chairs. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:- [Conf]
  3. James A. Kahle
    The Cell Processor Architecture. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:3- [Conf]
  4. David W. Oehmke, Nathan L. Binkert, Trevor N. Mudge, Steven K. Reinhardt
    How to Fake 1000 Registers. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:7-18 [Conf]
  5. Stephen Hines, Gary S. Tyson, David B. Whalley
    Reducing Instruction Fetch Cost by Packing Instructions into RegisterWindows. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:19-29 [Conf]
  6. Arvind Krishnaswamy, Rajiv Gupta
    Efficient Use of Invisible Registers in Thumb Code. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:30-42 [Conf]
  7. Hyesoon Kim, Onur Mutlu, Jared Stark, Yale N. Patt
    Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:43-54 [Conf]
  8. Pierre Salverda, Craig B. Zilles
    A Criticality Analysis of Clustering in Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:55-66 [Conf]
  9. Matt T. Yourst, Kanad Ghose
    Incremental Commit Groups for Non-Atomic Trace Processing. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:67-80 [Conf]
  10. Taku Ohsawa, Masamichi Takagi, Shoji Kawahara, Satoshi Matsushita
    Pinot: Speculative Multi-threading Processor Architecture Exploiting Parallelism over a Wide Range of Granularities. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:81-92 [Conf]
  11. Jiwei Lu, Abhinav Das, Wei-Chung Hsu, Khoa Nguyen, Santosh G. Abraham
    Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:93-104 [Conf]
  12. Guilherme Ottoni, Ram Rangan, Adam Stoler, David I. August
    Automatic Thread Extraction with Decoupled Software Pipelining. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:105-118 [Conf]
  13. Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasinghe
    Exploiting Vector Parallelism in Software Pipelined Loops. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:119-129 [Conf]
  14. Michael D. Bond, Kathryn S. McKinley
    Continuous Path and Edge Profiling. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:130-140 [Conf]
  15. David Hiniker, Kim M. Hazelwood, Michael D. Smith
    Improving Region Selection in Dynamic Optimization Systems. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:141-154 [Conf]
  16. Norman P. Jouppi
    The Future Evolution of High-Performance Microprocessors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:155- [Conf]
  17. Tingting Sha, Milo M. K. Martin, Amir Roth
    Scalable Store-Load Forwarding via Store Queue Index Prediction. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:159-170 [Conf]
  18. Sam S. Stone, Kevin M. Woley, Matthew I. Frank
    Address-Indexed Memory Disambiguation and Store-to-Load Forwarding. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:171-182 [Conf]
  19. Yuan Chou, Lawrence Spracklen, Santosh G. Abraham
    Store Memory-Level Parallelism Optimizations for Commercial Applications. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:183-196 [Conf]
  20. Fred A. Bower, Daniel J. Sorin, Sule Ozev
    A Mechanism for Online Diagnosis of Hard Faults in Microprocessors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:197-208 [Conf]
  21. Cyrus Bazeghi, Francisco J. Mesa-Martinez, Jose Renau
    uComplexity: Estimating Processor Design Effort. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:209-218 [Conf]
  22. Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott A. Mahlke
    Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:219-232 [Conf]
  23. Onur Mutlu, Hyesoon Kim, Yale N. Patt
    Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:233-244 [Conf]
  24. Meyrem Kirman, Nevin Kirman, José F. Martínez
    Cherry-MP: Correctly Integrating Checkpointed Early Resource Recycling in Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:245-256 [Conf]
  25. Smruti R. Sarangi, Wei Liu, Yuanyuan Zhou
    ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:257-270 [Conf]
  26. Qiang Wu, Margaret Martonosi, Douglas W. Clark, Vijay Janapa Reddi, Dan Connors, Youfeng Wu, Jin Lee, David Brooks
    A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:271-282 [Conf]
  27. Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail
    Thermal Management of On-Chip Caches Through Power Density Minimization. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:283-293 [Conf]
  28. Michael D. Powell, Ethan Schuchman, T. N. Vijaykumar
    Balancing Resource Utilization to Mitigate Power Density in Processor Pipelines. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:294-304 [Conf]
  29. Tzvetan S. Metodi, Darshan D. Thaker, Andrew W. Cross
    A Quantum Logic Array Microarchitecture: Scalable Quantum Data Movement and Computation. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:305-318 [Conf]
  30. Ronald D. Barnes, Shane Ryoo, Wen-mei W. Hwu
    "Flea-flicker" Multipass Pipelining: An Alternative to the High-Power Out-of-Order Offense. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:319-330 [Conf]
  31. Jan-Willem van de Waerdt, Stamatis Vassiliadis, Sanjeev Das, Sebastian Mirolo, Chris Yen, Bill Zhong, Carlos Basto, Jean-Paul van Itegem, Dinesh Amirtharaj, Kulbhushan Kalra, Pedro Rodriguez, Hans Van Antwerpen
    The TM3270 Media-Processor. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:331-342 [Conf]
  32. Jayanth Gummaraju, Mendel Rosenblum
    Stream Programming on General-Purpose Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:343-354 [Conf]
  33. Victor Moya Del Barrio, Carlos González, Jordi Roca, Agustin Fernández, Roger Espasa
    Shader Performance Analysis on a Modern GPU Architecture. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:355-364 [Conf]
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