Conferences in DBLP
Michael A. Schuette , John Paul Shen An Instruction-Level Performance Analysis of the Multiflow TRACE 14/300. [Citation Graph (0, 0)][DBLP ] Conf ] William Marcus Miller , Walid A. Najjar , A. P. Wim Böhm A Quantitative Analysis of Locality in Dataflow Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey C. Becker , Arvin Park , Matthew K. Farrens An Analysis of the Information Content of Address Reference Streams. [Citation Graph (0, 0)][DBLP ] Conf ] Pohua P. Chang , William Y. Chen , Scott A. Mahlke , Wen-mei W. Hwu Comparing Static and Dynamic Code Scheduling for Multiple-Instruction-Issue Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Butler , Yale N. Patt The Effect of Real Data Cache Behavior on the Performance of a Microarchitecture that Supports Dynamic Scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Brian K. Bray , Michael J. Flynn Strategies for Branch Target Buffers. [Citation Graph (0, 0)][DBLP ] Conf ] Tse-Yu Yeh , Yale N. Patt Two-Level Adaptive Training Branch Prediction. [Citation Graph (1, 0)][DBLP ] Conf ] Matthew K. Farrens , Arvin Park Workload and Implementation Considerations for Dynamic Base Register Caching. [Citation Graph (0, 0)][DBLP ] Conf ] William Y. Chen , Scott A. Mahlke , Pohua P. Chang , Wen-mei W. Hwu Data Access Microarchitectures for Superscalar Processors with Compiler-Assisted Data Prefetching. [Citation Graph (0, 0)][DBLP ] Conf ] Jan Hoogerbrugge , Henk Corporaal , Hans Mulder Software Pipelining for Transport-Triggered Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Reese B. Jones , Vicki H. Allan Software Pipelining: An Evaluation of Enhanced Pipelining. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Smotherman , Sanjay Krishnamurthy , P. S. Aravind , David Hunnicutt Efficient DAG Construction and Heuristic Calculation for Instruction Scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] David Bernstein , Doron Cohen , Hugo Krawczyk Code Duplication: An Assist for Global Instruction Scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Mauricio Breternitz Jr. , John Paul Shen Implementation Optimization Techniques for Architecture Synthesis of Application-Specific Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Ramesh Karri , Alex Orailoglu ALPS: An Algorithm for Pipeline Data Path Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Robert A. Walker , Shivkumar Ramabadran , Rajive Joshi , Steinar Flatland Increasing User Interaction During High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Gautam B. Singh GRIP: Graphics Reduced Instruction Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Bruce K. Holmer , Alvin M. Despain Viewing Instruction Set Design as an Optimization Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Mario Nemirovsky , Forrest Brewer , Roger C. Wood DISC: Dynamic Instruction Stream Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Haigeng Wang , Alexandru Nicolau , Roni Potasman A New Technique for Induction Variable Removal. [Citation Graph (0, 0)][DBLP ] Conf ] Gerben Essink , Emile H. L. Aarts , R. van Dongen , P. van Gerwen , Jan H. M. Korst , Kees A. Vissers Architecture and Programming of a VLIW Style Programmable Video Signal Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Fredrik Dahlgren , Per Stenström On Reconfigurable On-Chip Data Caches. [Citation Graph (0, 0)][DBLP ] Conf ] Sunah Lee , Rajiv Gupta Executing Loops on a Fine-Grained MIMD Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Steven J. Beaty Genetic Algorithms and Instruction Scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Bogong Su , Jian Wang GURPR* : A New Global Software Pipelining Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Samarina Makhdoom , Daniel Tabak , Richard Auletta Register/File/Cache Microarchitecture Study Using VHDL. [Citation Graph (0, 0)][DBLP ] Conf ] 