Conferences in DBLP
Scott Rixner , William J. Dally , Ujval J. Kapasi , Brucek Khailany , Abelardo López-Lagunas , Peter R. Mattson , John D. Owens A Bandwidth-efficient Architecture for Media Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Chia-Lin Yang , Barton Sano , Alvin R. Lebeck Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Corinna G. Lee , Mark G. Stoodley Simple Vector Microprocessors for Multimedia Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Ravi Bhargava , Lizy Kurian John , Brian L. Evans , Ramesh Radhakrishnan Evaluating MMX Technology Using DSP and Multimedia Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Sangwook P. Kim , Gary S. Tyson Analyzing the Working Set Characteristics of Branch Execution. [Citation Graph (0, 0)][DBLP ] Conf ] Alexandre Farcy , Olivier Temam , Roger Espasa , Toni Juan Dataflow Analysis of Branch Mispredictions and Its Application to Early Resolution of Branch Outcomes. [Citation Graph (0, 0)][DBLP ] Conf ] A. N. Eden , Trevor N. Mudge The YAGS Branch Prediction Scheme. [Citation Graph (0, 0)][DBLP ] Conf ] T. N. Vijaykumar , Gurindar S. Sohi Task Selection for a Multiscalar Processor. [Citation Graph (0, 0)][DBLP ] Conf ] SangMin Shim , Soo-Mook Moon Split-path Enhanced Pipeline Scheduling for Loops with Control Flows. [Citation Graph (0, 0)][DBLP ] Conf ] Erik Nystrom , Alexandre E. Eichenberger Effective Cluster Assignment for Modulo Scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Cliff Young , Michael D. Smith Better Global Scheduling Using Path Profiles. [Citation Graph (0, 0)][DBLP ] Conf ] Glenn Reinman , Brad Calder Predictive Techniques for Aggressive Load Speculation. [Citation Graph (0, 0)][DBLP ] Conf ] Ben-Chung Cheng , Daniel A. Connors , Wen-mei W. Hwu Compiler-Directed Early Load-Address Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Srikanth T. Srinivasan , Alvin R. Lebeck Load Latency Tolerance in Dynamically Scheduled Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Lambert Schaelicke , Al Davis Improving I/O Performance with a Conditional Store Buffer. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel H. Friendly , Sanjay J. Patel , Yale N. Patt Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Chi-Keung Luk , Todd C. Mowry Cooperative Prefetching: Compiler and Hardware Support for Effective Instruction Prefetching in Modern Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Guido Araujo , Paulo Centoducatte , Mario Cartes , Ricardo Pannain Code Compression Based on Operand Factorization. [Citation Graph (0, 0)][DBLP ] Conf ] Avinash Sodani , Gurindar S. Sohi Understanding the Differences Between Value Prediction and Instruction Reuse. [Citation Graph (0, 0)][DBLP ] Conf ] Stéphan Jourdan , Ronny Ronen , Michael Bekerman , Bishara Shomar , Adi Yoaz A Novel Renaming Scheme to Exploit Value Temporal Locality Through Physical Register Reuse and Unification. [Citation Graph (0, 0)][DBLP ] Conf ] Haitham Akkary , Michael A. Driscoll A Dynamic Multithreading Processor. [Citation Graph (0, 0)][DBLP ] Conf ] David López , Josep Llosa , Mateo Valero , Eduard Ayguadé Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Karel Driesen , Urs Hölzle The Cascaded Predictor: Economical and Adaptive Branch Target Prediction. [Citation Graph (0, 0)][DBLP ] Conf ] Kevin Skadron , Pritpal S. Ahuja , Margaret Martonosi , Douglas W. Clark Improving Prediction for Procedure Returns with Return-address-stack Repair Mechanisms. [Citation Graph (0, 0)][DBLP ] Conf ] John Kalamatianos , David R. Kaeli Predicting Indirect Branches via Data Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Mahmut T. Kandemir , Alok N. Choudhary , J. Ramanujam , Prithviraj Banerjee Improving Locality Using Loop and Data Transformations in an Integrated Framework. [Citation Graph (0, 0)][DBLP ] Conf ] Timothy Kong , Kent D. Wilken Precise Register Allocation for Irregular Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Emre Özer , Sanjeev Banerjia , Thomas M. Conte Unified Assign and Schedule: A New Approach to Scheduling for Clustered Register File Microarchitectures. [Citation Graph (0, 0)][DBLP ] Conf ] 