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Conferences in DBLP
- Chih-Chieh Lee, I-Cheng K. Chen, Trevor N. Mudge
The bi-Mode Branch Predictor. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:4-13 [Conf]
- Quinn Jacobson, Eric Rotenberg, James E. Smith
Path-Based Next Trace Prediction. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:14-23 [Conf]
- Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt
Alternative Fetch and Issue Policies for the Trace Cache Fetch Mechanism. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:24-33 [Conf]
- Jared Stark, Paul Racunas, Yale N. Patt
Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions into the Reservation Stations Out-of-Order. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:34-43 [Conf]
- Jude A. Rivers, Gary S. Tyson, Edward S. Davidson, Todd M. Austin
On High-Bandwidth Data Cache Design for Multi-Issue Processors. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:46-56 [Conf]
- Teresa L. Johnson, Matthew C. Merten, Wen-mei W. Hwu
Run-Time Spatial Locality Detection and Optimization. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:57-64 [Conf]
- G. P. Jones, Nigel P. Topham
A Comparison of Data Prefetching on an Access Decoupled and Superscalar Machine. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:65-70 [Conf]
- Nigel P. Topham, Antonio González, José González
The Design and Performance of a Conflict-Avoiding Cache. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:71-80 [Conf]
- James E. Bennett, Michael J. Flynn
Prediction Caches for Superscalar Processors. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:81-90 [Conf]
- David I. August, Wen-mei W. Hwu, Scott A. Mahlke
A Framework for Balancing Control Flow and Predication. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:92-103 [Conf]
- Seongbae Park, SangMin Shim, Soo-Mook Moon
Evaluation of Scheduling Techniques on a SPARC-based VLIW Testbed. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:104-113 [Conf]
- Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay S. Parekh, Dean M. Tullsen
Tuning Compiler Optimizations for Simultaneous Multithreading. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:114-124 [Conf]
- Milo M. K. Martin, Amir Roth, Charles N. Fischer
Exploiting Dead Value Information. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:125-135 [Conf]
- Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, James E. Smith
Trace Processors. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:138-148 [Conf]
- Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic
The Multicluster Architecture: Reducing Cycle Time Through Partitioning. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:149-159 [Conf]
- Roger Espasa, Mateo Valero, James E. Smith
Out-of-Order Vector Architectures. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:160-170 [Conf]
- Corinna G. Lee, Derek J. DeVries
Initial Results on the Performance and Cost of Vector Microprocessors. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:171-182 [Conf]
- Johnson Kin, Munish Gupta, William H. Mangione-Smith
The Filter Cache: An Energy Efficient Memory Structure. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:184-193 [Conf]
- Charles Lefurgy, Peter L. Bird, I-Cheng K. Chen, Trevor N. Mudge
Improving Code Density Using Compression Techniques. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:194-203 [Conf]
- Darko Kirovski, Johnson Kin, William H. Mangione-Smith
Procedure Based Program Compression. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:204-213 [Conf]
- Gary S. Tyson, Todd M. Austin
Improving the Accuracy and Performance of Memory Communication Through Renaming. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:218-227 [Conf]
- Chung-Ho Chen, Akida Wu
Microarchitecture Support for Improving the Performance of Load Target Prediction. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:228-234 [Conf]
- Andreas Moshovos, Gurindar S. Sohi
Streamlining Inter-Operation Memory Communication via Data Dependence Prediction. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:235-245 [Conf]
- Yiannakis Sazeides, James E. Smith
The Predictability of Data Values. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:248-258 [Conf]
- Brad Calder, Peter Feller, Alan Eustace
Value Profiling. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:259-269 [Conf]
- Freddy Gabbay, Avi Mendelson
Can Program Profiling Support Value Prediction? [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:270-280 [Conf]
- Kai Wang, Manoj Franklin
Highly Accurate Data Value Prediction Using Hybrid Predictors. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:281-290 [Conf]
- Jeffrey Dean, James E. Hicks, Carl A. Waldspurger, William E. Weihl, George Z. Chrysos
ProfileMe: Hardware Support for Instruction-Level Profiling on Out-of-Order Processors. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:292-302 [Conf]
- Nicholas C. Gloy, Trevor Blackwell, Michael D. Smith, Brad Calder
Procedure Placement Using Temporal Ordering Information. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:303-313 [Conf]
- Todd C. Mowry, Chi-Keung Luk
Predicting Data Cache Misses in Non-Numeric Applications through Correlation Profiling. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:314-320 [Conf]
- Heng Liao, Andrew Wolfe
Available Parallelism in Video Applications. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:321-329 [Conf]
- Chunho Lee, Miodrag Potkonjak, William H. Mangione-Smith
MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communicatons Systems. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:330-335 [Conf]
- F. Jesús Sánchez, Antonio González
Cache Sensitive Modulo Scheduling. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:338-348 [Conf]
- Steve Carr, Yiping Guan
Unroll-and-Jam Using Uniformly Generated Sets. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:349-357 [Conf]
- Rajiv Gupta, David A. Berson, Jesse Zhixi Fang
Resource-Sensitive Profile-Directed Data Flow Analysis for Code Optimization. [Citation Graph (0, 0)][DBLP]
MICRO, 1997, pp:358-368 [Conf]
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