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Conferences in DBLP

International Symposium on Microarchitecture (MICRO) (micro)
2006 (conf/micro/2006)

  1. Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee
    A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:3-14 [Conf]
  2. Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonathan Adams, Hai Zhou
    Yield-Aware Cache Architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:15-25 [Conf]
  3. Smruti R. Sarangi, Abhishek Tiwari, Josep Torrellas
    Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:26-37 [Conf]
  4. Shan Lu, Pin Zhou, Wei Liu, Yuanyuan Zhou, Josep Torrellas
    PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:38-52 [Conf]
  5. Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt
    Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:53-64 [Conf]
  6. Bertrand A. Maher, Aaron Smith, Doug Burger, Kathryn S. McKinley
    Merging Head and Tail Duplication for Convergent Hyperblock Formation. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:65-76 [Conf]
  7. Mark Heffernan, Kent D. Wilken, Ghassan Shobaki
    Data-Dependency Graph Transformations for Superblock Scheduling. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:77-88 [Conf]
  8. Aaron Smith, Ramadass Nagarajan, Karthikeyan Sankaralingam, Robert G. McDonald, Doug Burger, Stephen W. Keckler, Kathryn S. McKinley
    Dataflow Predication. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:89-102 [Conf]
  9. Weidong Shi, Hsien-Hsin S. Lee
    Authentication Control Point and Its Implications For Secure Processor Design. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:103-112 [Conf]
  10. Xiaotong Zhuang, Tao Zhang, Santosh Pande
    Using Branch Correlation to Identify Infeasible Paths for Anomaly Detection. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:113-122 [Conf]
  11. Kun Zhang, Tao Zhang, Santosh Pande
    Memory Protection through Dynamic Access Control. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:123-134 [Conf]
  12. Feng Qin, Cheng Wang, Zhenmin Li, Ho-Seop Kim, Yuanyuan Zhou, Youfeng Wu
    LIFT: A Low-Overhead Practical Information Flow Tracking System for Detecting Security Attacks. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:135-148 [Conf]
  13. Ron Gabor, Shlomo Weiss, Avi Mendelson
    Fairness and Throughput in Switch on Event Multithreading. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:149-160 [Conf]
  14. P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthaveetil
    A Predictive Performance Model for Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:161-170 [Conf]
  15. Anne Bracy, Amir Roth
    Serialization-Aware Mini-Graphs: Performance with Fewer Resources. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:171-184 [Conf]
  16. Bratin Saha, Ali-Reza Adl-Tabatabai, Quinn Jacobson
    Architectural Support for Software Transactional Memory. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:185-196 [Conf]
  17. Banit Agrawal, Timothy Sherwood
    Virtually Pipelined Network Memory. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:197-207 [Conf]
  18. Kyle J. Nesbit, Nidhi Aggarwal, James Laudon, James E. Smith
    Fair Queuing Memory Systems. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:208-222 [Conf]
  19. Jared C. Smolens, Brian T. Gold, Babak Falsafi, James C. Hoe
    Reunion: Complexity-Effective Multicore Redundancy. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:223-234 [Conf]
  20. Jack Sampson, Rubén González, Jean-Francois Collard, Norman P. Jouppi, Mike Schlansker, Brad Calder
    Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:235-246 [Conf]
  21. Pierre Palatin, Yves Lhuillier, Olivier Temam
    CAPSULE: Hardware-Assisted Parallel Execution of Component-Based Programs. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:247-258 [Conf]
  22. Ram Rangan, Neil Vachharajani, Adam Stoler, Guilherme Ottoni, David I. August, George Z. N. Cai
    Support for High-Frequency Streaming in CMPs. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:259-272 [Conf]
  23. Samantika Subramaniam, Gabriel H. Loh
    Fire-and-Forget: Load/Store Scheduling with No Store Queue at All. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:273-284 [Conf]
  24. Tingting Sha, Milo M. K. Martin, Amir Roth
    NoSQ: Store-Load Communication without a Store Queue. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:285-296 [Conf]
  25. Fernando Castro, Luis Piñuel, Daniel Chaver, Manuel Prieto, Michael C. Huang, Francisco Tirado
    DMDC: Delayed Memory Dependence Checking through Age-Based Filtering. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:297-308 [Conf]
  26. Michael R. Marty, Mark D. Hill
    Coherence Ordering for Ring-based Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:309-320 [Conf]
  27. Noel Eisley, Li-Shiuan Peh, Li Shang
    In-Network Cache Coherence. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:321-332 [Conf]
  28. Chrysostomos Nicopoulos, Dongkook Park, Jongman Kim, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das
    ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:333-346 [Conf]
  29. Canturk Isci, Alper Buyuktosunoglu, Chen-Yong Cher, Pradip Bose, Margaret Martonosi
    An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:347-358 [Conf]
  30. Canturk Isci, Gilberto Contreras, Margaret Martonosi
    Live, Runtime Phase Monitoring and Prediction on Real Systems with Application to Dynamic Power Management. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:359-370 [Conf]
  31. Ahmed Youssef, Mohab Anis, Mohamed I. Elmasry
    Dynamic Standby Prediction for Leakage Tolerant Microprocessor Functional Units. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:371-384 [Conf]
  32. Ranjith Subramanian, Yannis Smaragdakis, Gabriel H. Loh
    Adaptive Caches: Effective Shaping of Cache Behavior to Workloads. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:385-396 [Conf]
  33. Ibrahim Hur, Calvin Lin
    Memory Prefetching Using Adaptive Stream Detection. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:397-408 [Conf]
  34. James Tuck, Luis Ceze, Josep Torrellas
    Scalable Cache Miss Handling for High Memory-Level Parallelism. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:409-422 [Conf]
  35. Moinuddin K. Qureshi, Yale N. Patt
    Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:423-432 [Conf]
  36. Keshavan Varadarajan, S. K. Nandy, Vishal Sharda, Amrutur Bharadwaj, Ravi R. Iyer, Srihari Makineni, Donald Newell
    Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:433-442 [Conf]
  37. Bradford M. Beckmann, Michael R. Marty, David A. Wood
    ASR: Adaptive Selective Replication for CMP Caches. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:443-454 [Conf]
  38. Sangyeun Cho, Lei Jin
    Managing Distributed, Shared L2 Caches through OS-Level Page Allocation. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:455-468 [Conf]
  39. Bryan Black, Murali Annavaram, Ned Brekelbaum, John DeVale, Lei Jiang, Gabriel H. Loh, Don McCaule, Pat Morrow, Donald W. Nelson, Daniel Pantuso, Paul Reed, Jeff Rupley, Sadasivan Shankar, John Shen, Clair Webb
    Die Stacking (3D) Microarchitecture. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:469-479 [Conf]
  40. Karthikeyan Sankaralingam, Ramadass Nagarajan, Robert G. McDonald, Rajagopalan Desikan, Saurabh Drolia, M. S. Govindan, Paul Gratz, Divya Gulati, Heather Hanson, Changkyu Kim, Haiming Liu, Nitya Ranganathan, Simha Sethumadhavan, Sadia Sharif, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger
    Distributed Microarchitectural Protocols in the TRIPS Prototype Processor. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:480-491 [Conf]
  41. Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, José F. Martínez, Alyssa B. Apsel, Matthew A. Watkins, David H. Albonesi
    Leveraging Optical Technology in Future Bus-based Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:492-503 [Conf]
  42. Xiaoyao Liang, David Brooks
    Mitigating the Impact of Process Variations on Processor Register Files and Execution Units. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:504-514 [Conf]
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