Conferences in DBLP

Mathematical Science Institute Workshops (msiw)
1989 (conf/msiw/1989)

1. George J. Milne
   Design for Verifiability. [Citation Graph (0, 0)][DBLP]
   Hardware Specification, Verification and Synthesis, 1989, pp:1-13 [Conf]
   
2. Randal E. Bryant
   Verification of Synchronous Circuits by Symbolic Logic Simulation. [Citation Graph (0, 0)][DBLP]
   Hardware Specification, Verification and Synthesis, 1989, pp:14-24 [Conf]
   
3. Daniel Weise
   Constraints, Abstraction and Verification. [Citation Graph (0, 0)][DBLP]
   Hardware Specification, Verification and Synthesis, 1989, pp:25-39 [Conf]
   
4. Brian T. Graham, Graham M. Birtwistle
   Formalising the Design of an SECD chip. [Citation Graph (0, 0)][DBLP]
   Hardware Specification, Verification and Synthesis, 1989, pp:40-66 [Conf]
   
5. Paul Loewenstein
   Reasoning about State Machines in Higher-Order Logic. [Citation Graph (0, 0)][DBLP]
   Hardware Specification, Verification and Synthesis, 1989, pp:67-89 [Conf]
   
6. Christian Lengauer, Bikash Sabata, Farshid Arman
   A Mechanically Derived Systolic Implementation of Pyramid Initialization. [Citation Graph (0, 0)][DBLP]
   Hardware Specification, Verification and Synthesis, 1989, pp:90-105 [Conf]
   
7. Raul Camposano
   Behavior-Preserving Transformations for High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
   Hardware Specification, Verification and Synthesis, 1989, pp:106-128 [Conf]
   
8. Geoffrey M. Brown, Miriam Leeser
   From Programs to Transistors: Verifying Hardware Synthesis Tools. [Citation Graph (0, 0)][DBLP]
   Hardware Specification, Verification and Synthesis, 1989, pp:129-151 [Conf]
   
9. Shiu-Kai Chin
   Combining Engineering Vigor with Mathematical Rigor. [Citation Graph (0, 0)][DBLP]
   Hardware Specification, Verification and Synthesis, 1989, pp:152-176 [Conf]
   
10. Jeffrey J. Joyce
    Totally Verified Systems: Linking Verified Software to Verified Hardware. [Citation Graph (0, 0)][DBLP]
    Hardware Specification, Verification and Synthesis, 1989, pp:177-201 [Conf]
    
11. P. A. Subrahmanyam
    What's in a Timing Discipline? Considerations in the Specification and Synthesis of Systems with Interacting Asynchronous and Synchronous Components. [Citation Graph (0, 0)][DBLP]
    Hardware Specification, Verification and Synthesis, 1989, pp:202-223 [Conf]
    
12. David L. Dill
    Complete Trace Structures. [Citation Graph (0, 0)][DBLP]
    Hardware Specification, Verification and Synthesis, 1989, pp:224-243 [Conf]
    
13. Alain J. Martin
    The Design of a Delay-Insensitive Microprocessor: An Example of Circuit Synthesis by Program Transformation. [Citation Graph (0, 0)][DBLP]
    Hardware Specification, Verification and Synthesis, 1989, pp:244-259 [Conf]
    
14. Steven D. Johnson
    Manipulating Logical Organization with System Factorizations. [Citation Graph (0, 0)][DBLP]
    Hardware Specification, Verification and Synthesis, 1989, pp:260-281 [Conf]
    
15. Warren A. Hunt Jr., Bishop Brock
    The Verification of a Bit-slice ALU. [Citation Graph (0, 0)][DBLP]
    Hardware Specification, Verification and Synthesis, 1989, pp:282-306 [Conf]
    
16. Mark Bickford, Mandayam K. Srivas
    Verification of a Pipelined Microprocessor Using Clio. [Citation Graph (0, 0)][DBLP]
    Hardware Specification, Verification and Synthesis, 1989, pp:307-332 [Conf]
    
17. David A. Basin, Peter Del Vecchio
    Verification Of Combinational Logic in Nuprl. [Citation Graph (0, 0)][DBLP]
    Hardware Specification, Verification and Synthesis, 1989, pp:333-357 [Conf]
    
18. F. Keith Hanna, Neil Daeche, Mark Longley
    Veritas⁺: A Specification Language Based on Type Theory. [Citation Graph (0, 0)][DBLP]
    Hardware Specification, Verification and Synthesis, 1989, pp:358-379 [Conf]
    
19. Mary Sheeran
    Categories for the Working Hardware Designer. [Citation Graph (0, 0)][DBLP]
    Hardware Specification, Verification and Synthesis, 1989, pp:380-402 [Conf]