Conferences in DBLP

Memory Technology, Design and Testing (mtdt)
2006 (conf/mtdt/2006)

1. 
   Reviewers. [Citation Graph (0, 0)][DBLP]
   MTDT, 2006, pp:- [Conf]
   
2. 
   Foreword. [Citation Graph (0, 0)][DBLP]
   MTDT, 2006, pp:- [Conf]
   
3. Jordan Lai
   SRAM Design Techniques for Sub-nano CMOS Technology. [Citation Graph (0, 0)][DBLP]
   MTDT, 2006, pp:- [Conf]
   
4. Chih-Yuan Lu
   Non-volatile Semiconductor Memory Technology in Nanotech Era. [Citation Graph (0, 0)][DBLP]
   MTDT, 2006, pp:- [Conf]
   
5. 
   Organizing Committee. [Citation Graph (0, 0)][DBLP]
   MTDT, 2006, pp:- [Conf]
   
6. Charles Hsu
   Future Prospective of Programmable Logic Non-volatile Device. [Citation Graph (0, 0)][DBLP]
   MTDT, 2006, pp:- [Conf]
   
7. Riichiro Shirota
   Roadmap of the Flash Memory. [Citation Graph (0, 0)][DBLP]
   MTDT, 2006, pp:- [Conf]
   
8. Peter Muhmenthaler
   New on-Chip DFT and ATE Features for Efficient Embedded Memory Test. [Citation Graph (0, 0)][DBLP]
   MTDT, 2006, pp:- [Conf]
   
9. Mohamed Azimane
   High-Quality Memory Test. [Citation Graph (0, 0)][DBLP]
   MTDT, 2006, pp:- [Conf]
   
10. 
    Program Committee. [Citation Graph (0, 0)][DBLP]
    MTDT, 2006, pp:- [Conf]
    
11. Pei-Lin Pai
    DRAM Industry Trend. [Citation Graph (0, 0)][DBLP]
    MTDT, 2006, pp:- [Conf]
    
12. Mu-Hsien Hsu, Yu-Tsao Hsing, Jen-Chieh Yeh, Cheng-Wen Wu
    Fault-Pattern Oriented Defect Diagnosis for Flash Memory. [Citation Graph (0, 0)][DBLP]
    MTDT, 2006, pp:3-8 [Conf]
    
13. T. A. Gyonjyan, Gurgen Harutunyan, Valery A. Vardanian
    A March-Based Algorithm for Location and Full Diagnosis of All Unlinked Static Faults. [Citation Graph (0, 0)][DBLP]
    MTDT, 2006, pp:9-14 [Conf]
    
14. Hsing-Chung Liang, Le-Quen Tzeng
    Improved Representatives for Unrepairability Judging and Economic Repair Solutions of Memories. [Citation Graph (0, 0)][DBLP]
    MTDT, 2006, pp:15- [Conf]
    
15. Jyi-Tsong Lin, Mike Chang
    A New 1T DRAM Cell With Enhanced Floating Body Ef. [Citation Graph (0, 0)][DBLP]
    MTDT, 2006, pp:23-27 [Conf]
    
16. Ding-Ming Kwai, Yung-Fa Chou, Meng-Fan Chang, Su-Meng Yang, Ding-Sheng Chen, Min-Chung Hsu, Yu-Zhen Liao, Shiao-Yi Lin, Yu-Ling Sung, Chia-Hsin Lee, Hsin-Kun Hsu
    FlexiVia ROM Compiler Programmable on Different Via Layers Based on Top Metal Assignment. [Citation Graph (0, 0)][DBLP]
    MTDT, 2006, pp:28-33 [Conf]
    
17. Shen-Fu Hsiao, Yo-Chi Chen, Ming-Yu Tsai, Tze-Chong Cheng
    Novel Memory Organization and Circuit Designs for Efficient Data Access in Applications of 3D Graphics and Multimedia Coding. [Citation Graph (0, 0)][DBLP]
    MTDT, 2006, pp:34-42 [Conf]
    
18. Yuui Shimizu, Hisanori Aikawa, Keiji Hosotani, Naoharu Shimomura, Tadashi Kai, Yoshihiro Ueda, Yoshiaki Asao, Yoshihisa Iwata, Kenji Tsuchida, Sumio Ikegawa
    MRAM Write Error Categorization with QCKB. [Citation Graph (0, 0)][DBLP]
    MTDT, 2006, pp:43-48 [Conf]
    
19. Jörg E. Vollrath, Jürg Schwizer, Marcin Gnat, Ralf Schneider, Bret Johnson
    DDR2 DRAM Output Timing Optimization. [Citation Graph (0, 0)][DBLP]
    MTDT, 2006, pp:49-54 [Conf]
    
20. Mohammad Sharifkhani, Shah M. Jahinuzzaman, Manoj Sachdev
    Dynamic Data Stability in SRAM Cells and Its Implications on Data Stability Tests. [Citation Graph (0, 0)][DBLP]
    MTDT, 2006, pp:55-64 [Conf]
    
21. Ding-Ming Kwai, Ching-Hua Hsiao, Chung-Ping Kuo, Chi-Hsien Chuang, Min-Chung Hsu, Yi-Chun Chen, Yu-Ling Sung, Hsien-Yu Pan, Chia-Hsin Lee, Meng-Fan Chang, Yung-Fa Chou
    SRAM Cell Current in Low Leakage Design. [Citation Graph (0, 0)][DBLP]
    MTDT, 2006, pp:65-70 [Conf]
    
22. Hua Wang, Miguel Miranda, Francky Catthoor, Wim Dehaene
    On the Combined Impact of Soft and Medium Gate Oxide Breakdown and Process Variability on the Parametric Figures of SRAM components. [Citation Graph (0, 0)][DBLP]
    MTDT, 2006, pp:71-76 [Conf]
    
23. Victor Chao-Wei Kuo, Chih-Ming Chao, Chih-Kai Kang, Li-Wei Liu, Tzung-Bin Huang, Liang-Tai Kuo, Shi-Hsien Chen, Houng-Chi Wei, Hann-Ping Hwang, Saysamone Pittikoun
    Detailed Comparisons of Program, Erase and Data Retention Characteristics between P+- and N+-Poly SONOS NAND Flash Memory. [Citation Graph (0, 0)][DBLP]
    MTDT, 2006, pp:77-79 [Conf]
    
24. Jia-Lin Wu, Hua-Ching Chien, Chien-Wei Liao, Cheng-Yen Wu, Chih-Yuan Lee, Houng-Chi Wei, Shih-Hsien Chen, Hann-Ping Hwang, Saysamone Pittikoun, Travis Cho, Chin-Hsing Kao
    Comparison of Electrical and Reliability Characteristics of Different Tunnel Oxides in SONOS Flash Memory. [Citation Graph (0, 0)][DBLP]
    MTDT, 2006, pp:80-84 [Conf]