Conferences in DBLP

Memory Technology, Design and Testing (mtdt)
1999 (conf/mtdt/1999)

1. Martin Margala
   Low Power SRAMs for Battery Operation. [Citation Graph (0, 0)][DBLP]
   MTDT, 1999, pp:6-0 [Conf]
   
2. Luke Roth, Lee D. Coraor, David L. Landis, Paul T. Hulina, Scott Deno
   Computing in Memory Architectures for Digital Image Processing. [Citation Graph (0, 0)][DBLP]
   MTDT, 1999, pp:8-15 [Conf]
   
3. David L. Rhodes, Wayne Wolf
   Unbalanced Cache Systems. [Citation Graph (0, 0)][DBLP]
   MTDT, 1999, pp:16-23 [Conf]
   
4. G. Jack Lipovski, Clement T. Yu
   The Dynamic Associative Access Memory Chip and Its Application to SIMD Processing and Full-Text Database Retrieval. [Citation Graph (0, 0)][DBLP]
   MTDT, 1999, pp:24-0 [Conf]
   
5. Sue Brown, Jeff Campbell, Sherri Griffin, Dick James, Ray Haythornthwaite
   Failure Mechanisms Detected in Memory Chips during Routine Construction Analysis. [Citation Graph (0, 0)][DBLP]
   MTDT, 1999, pp:34-39 [Conf]
   
6. Jun Zhao, Fred J. Meyer, Fabrizio Lombardi
   Interconnect Diagnosis of Bus-Connected Multi-RAM Systems. [Citation Graph (0, 0)][DBLP]
   MTDT, 1999, pp:40-47 [Conf]
   
7. Julie D. Segal, Sergei Bakarian, Jonathon E. Colburn, Madan Kumar, Chang Hong, Alex Shubat
   Determining Redundancy Requirements for Memory Arrays with Critical Area Analysis. [Citation Graph (0, 0)][DBLP]
   MTDT, 1999, pp:48-53 [Conf]
   
8. Doug Malone
   Design Validation of .18 um 1 Ghz Cache and Register Arrays. [Citation Graph (0, 0)][DBLP]
   MTDT, 1999, pp:54-0 [Conf]
   
9. Jörg E. Vollrath
   Tutorial: Characterizing SDRAMS. [Citation Graph (0, 0)][DBLP]
   MTDT, 1999, pp:62-0 [Conf]
   
10. Larry Fenstermaker, Ilyoung Kim, Jim L. Lewandowski, Jeffrey J. Nagy
    Built In Self Test for Ring Addressed FIFOs with Transparent Latches. [Citation Graph (0, 0)][DBLP]
    MTDT, 1999, pp:72-77 [Conf]
    
11. Raju Khubchandani
    A Fast Test to Generate Flash Memory Threshold Voltage Distribution Map. [Citation Graph (0, 0)][DBLP]
    MTDT, 1999, pp:78-82 [Conf]
    
12. Piotr R. Sidorowicz
    Modeling and Testing Transistor Faults in Content-Addressable Memories. [Citation Graph (0, 0)][DBLP]
    MTDT, 1999, pp:83-90 [Conf]
    
13. Daniel P. Van der Velde, A. J. van de Goor
    Designing a Memory Module Tester. [Citation Graph (0, 0)][DBLP]
    MTDT, 1999, pp:91-0 [Conf]
    
14. Gershom Birk, Duncan G. Elliott, Bruce F. Cockburn
    A Comparative Simulation Study of Four Multilevel DRAMs. [Citation Graph (0, 0)][DBLP]
    MTDT, 1999, pp:102-109 [Conf]
    
15. Mark Brehob, Richard J. Enbody
    The Potential of Carbon-Based Memory Systems. [Citation Graph (0, 0)][DBLP]
    MTDT, 1999, pp:110-114 [Conf]
    
16. Martin Margala
    Low-Power SRAM Circuit Design. [Citation Graph (0, 0)][DBLP]
    MTDT, 1999, pp:115-122 [Conf]
    
17. Betty Prince
    A Tribute to Graphics Drams. [Citation Graph (0, 0)][DBLP]
    MTDT, 1999, pp:123-0 [Conf]