Conferences in DBLP
Ray Haythornthwaite Failure Mechanisms in Semiconductor Memory Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jun Zhao , Fred J. Meyer , Fabrizio Lombardi Diagnosing the Interconnect of Bus-Connected Multi-RAM Systems under Restricted and General Fault Models. [Citation Graph (0, 0)][DBLP ] Conf ] Alvin Jee , Jonathon E. Colburn , V. Swamy Irrinki , Mukesh Puri Optimizing Memory Tests by Analyzing Defect Coverage. [Citation Graph (0, 0)][DBLP ] Conf ] Rino Micheloni , Matteo Zammattio , Giovanni Campardo , Osama Khouri , Guido Torelli Hierarchical Sector Biasing Organization for Flash Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Osama Khouri , Rino Micheloni , Stefano Gregori , Guido Torelli Fast Voltage Regulator for Multilevel Flash Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Jean Michel Daga , Caroline Papaix , Marc Merandat , Stephane Ricard , Giuseppe Medulla , Jeanine Guichaoua , Daniel Auvergne Design Techniques for Embedded EEPROM Memories in Portable ASIC and ASSP Solutions. [Citation Graph (0, 0)][DBLP ] Conf ] Ruili Zhang , William C. Black Jr. , Marwan M. Hassoun Windowed MRAM Sensing Scheme. [Citation Graph (0, 0)][DBLP ] Conf ] Jörg E. Vollrath Synchronous Dynamic Memory Test Construction: A Field Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Kamal Rajkanan Yield Analysis Methodology for Low Defectivity Wafer Fabs. [Citation Graph (0, 0)][DBLP ] Conf ] Said Hamdioui , A. J. van de Goor , Mike Rodgers , David Eastwick March Tests for Realistic Faults in Two-Port Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Khoan Truong A Simple Built-In Self Test For Dual Ported SRAMs. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Redeker , Markus Rudack , Thomas Lobbe , Dirk Niggemeyer Using GLFSRs for Pseudo-Random Memory BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Tsong Shiue Optimizing Memory Bandwidth with ILP Based Memory Exploration and Assignment for Low Power Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Valerie Lines , Abdullah Ahmed , Peter Ma , Stanley Ma , Robert McKenzie , Hong-Seok Kim , Cynthia Mar 66MHz 2.3M Ternary Dynamic Content Addressable Memory. [Citation Graph (0, 0)][DBLP ] Conf ] C. Frey , F. Genevaux , C. Issartel , D. Turgis , Jean-Pierre Schoellkopf A Low Voltage Embedded Single Port SRAM Generator in a 0.18µm Standard CMOS Process. [Citation Graph (0, 0)][DBLP ] Conf ] Dirk Niggemeyer , Elizabeth M. Rudnick , Michael Redeker Diagnostic Testing of Embedded Memories Based on Output Tracing. [Citation Graph (0, 0)][DBLP ] Conf ] Kamran Zarrineh , R. Dean Adams , Aneesha P. Deo Defect Analysis and Realistic Fault Model Extensions for Static Random Access Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Zemo Yang , Samiha Mourad Crosstalk in Deep Submicron DRAMs. [Citation Graph (0, 0)][DBLP ] Conf ] 