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Conferences in DBLP

Memory Technology, Design and Testing (mtdt)
2004 (conf/mtdt/2004)

  1. Elaine Ou, Woodward Yang
    Fast Error-Correcting Circuits for Fault-Tolerant Memory. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:8-12 [Conf]
  2. Adil Akaaboune, Nazeih Botros, Jaafar Alghazo
    Tag Skipping Technique Using WTS Buffer for Optimal Low Power Cache Design. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:13-18 [Conf]
  3. Jaafar Alghazo, Adil Akaaboune, Nazeih Botros
    SF-LRU Cache Replacement Algorithm. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:19-24 [Conf]
  4. A. J. van de Goor, Said Hamdioui, Zaid Al-Ars
    The Effectiveness of the Scan Test and Its New Variants. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:26-31 [Conf]
  5. Zaid Al-Ars, Martin Herzog, Ivo Schanstra, A. J. van de Goor
    Influence of Bit Line Twisting on the Faulty Behavior of DRAMs. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:32-37 [Conf]
  6. Luca Schiano, Marco Ottavi, Fabrizio Lombardi
    Markov Models of Fault-Tolerant Memory Systems under SEU. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:38-43 [Conf]
  7. Bruce F. Cockburn
    Tutorial on Magnetic Tunnel Junction Magnetoresistive Random-Access Memory. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:46-51 [Conf]
  8. Said Hamdioui, Georgi Gaydadjiev, A. J. van de Goor
    The State-of-Art and Future Trends in Testing Embedded Memories. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:54-59 [Conf]
  9. Shyue-Kung Lu, Shih-Chang Huang
    Built-in Self-Test and Repair (BISTR) Techniques for Embedded RAMs. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:60-64 [Conf]
  10. Li-Ming Denq, Rei-Fu Huang, Cheng-Wen Wu, Yeong-Jar Chang, Wen Ching Wu
    A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:65-69 [Conf]
  11. Rita Zappa, Carolina Selva, Danilo Rimondi, Cosimo Torelli, M. Crestan, Giovanni Mastrodomenico, Lara Albani
    Micro Programmable Built-In Self Repair for SRAMs. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:72-77 [Conf]
  12. Swapnil Bahl
    A Novel Method for Silicon Configurable Test Flow and Algorithms for Testing, Debugging and Characterizing Different Types of Embedded Memories through a Shared Controller. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:78-83 [Conf]
  13. Carolina Selva, Cosimo Torelli, Danilo Rimondi, Rita Zappa, Stefano Corbani, Giovanni Mastrodomenico, Lara Albani
    A Programmable Built-in Self-Diagnosis for Embedded SRAM. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:84-89 [Conf]
  14. R. Dean Adams, Robert Abbott, Xiaoliang Bai, Dwayne Burek, Eric MacDonald
    An Integrated Memory Self Test and EDA Solution. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:92-95 [Conf]
  15. Saman Adham, Benoit Nadeau-Dostie
    A BIST Algorithm for Bit/Group Write Enable Faults in SRAMs. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:98-101 [Conf]
  16. N. Derhacobian, Valery A. Vardanian, Yervant Zorian
    Embedded Memory Reliability: The SER Challenge. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:104-110 [Conf]
  17. Michael Spica, T. M. Mak
    Do We Need Anything More Than Single Bit Error Correction (ECC)? [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:111-116 [Conf]
  18. Rob Aitken
    Redundancy & It's Not Just for Defects Anymore. [Citation Graph (0, 0)][DBLP]
    MTDT, 2004, pp:117-120 [Conf]
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