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Conferences in DBLP

Memory Technology, Design and Testing (mtdt)
2001 (conf/mtdt/2001)

  1. G. Harling
    A DRAM Compiler for Fully Optimized Memory Instances. [Citation Graph (0, 0)][DBLP]
    MTDT, 2001, pp:3-8 [Conf]
  2. Kyung-Saeng Kim, KwangMyoung Rho, Kwyro Lee
    Orthogonal Transpose-RAM Cell Array Architecture with Alternate Bit-Line To Bit-Line Contact Scheme. [Citation Graph (0, 0)][DBLP]
    MTDT, 2001, pp:9-12 [Conf]
  3. Raymond J. Sung, John C. Koob, Tyler L. Brandon, Duncan G. Elliott, Bruce F. Cockburn
    Design of an Embedded Fully-Depleted SOI SRAM. [Citation Graph (0, 0)][DBLP]
    MTDT, 2001, pp:13-0 [Conf]
  4. Sandeep Koranne, Tom Waayers, Robert Beurze, Clemens Wouters, Sunil Kumar, G. S. Visweswara
    A P1500 Compliant Programable BistShell for Embedded Memories. [Citation Graph (0, 0)][DBLP]
    MTDT, 2001, pp:21-28 [Conf]
  5. Brian R. Kessler, Jeffrey Dreibelbis, Tim McMahon, Joshua S. McCloy, Rex Kho
    BIST-Based Bitfail Mapping of an Embedded DRAM. [Citation Graph (0, 0)][DBLP]
    MTDT, 2001, pp:29-0 [Conf]
  6. S. Matarrese, L. Fasoli
    A Method to Caculate Redundancy Coverage for FLASH Memory. [Citation Graph (0, 0)][DBLP]
    MTDT, 2001, pp:41-44 [Conf]
  7. Stefano Gregori, Guido Torelli, Osama Khouri, Rino Micheloni
    An Error Control Code Scheme for Multilevel Flash Memories. [Citation Graph (0, 0)][DBLP]
    MTDT, 2001, pp:45-50 [Conf]
  8. Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian
    An Approach for Evaluation of Redunancy Analysis Algorithms. [Citation Graph (0, 0)][DBLP]
    MTDT, 2001, pp:51-0 [Conf]
  9. Zaid Al-Ars, A. J. van de Goor
    Transient Faults in DRAMs: Concepts, Analysis and Impact on Tests. [Citation Graph (0, 0)][DBLP]
    MTDT, 2001, pp:59-64 [Conf]
  10. Said Hamdioui, A. J. van de Goor, David Eastwick, Mike Rodgers
    Realistic Fault Models and Test Procedures for Multi-Port SRAMs. [Citation Graph (0, 0)][DBLP]
    MTDT, 2001, pp:65-72 [Conf]
  11. Farzin Karimi, Fabrizio Lombardi, V. Swamy Irrinki, T. Crosby
    A Parallel Approach for Testing Multi-Port Static Random Access Memories. [Citation Graph (0, 0)][DBLP]
    MTDT, 2001, pp:73-0 [Conf]
  12. Simon Napper, Dian Yang
    Equivalence Checking a 256MB SDRAM. [Citation Graph (0, 0)][DBLP]
    MTDT, 2001, pp:85-90 [Conf]
  13. Xiaoling Sun, Jian Xu, Pieter M. Trouborst
    Testing Carry Logic Modules of SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP]
    MTDT, 2001, pp:91-98 [Conf]
  14. Osama Khouri, Stefano Gregori, Dario Soltesz, Guido Torelli, Rino Micheloni
    Low Output Resistance Charge Pump for Flash Memory Programming. [Citation Graph (0, 0)][DBLP]
    MTDT, 2001, pp:99-0 [Conf]
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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002