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Conferences in DBLP
- A. Kablanian
Embedded Memory Test and Repair. [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:- [Conf]
- Michael Nicolaidis
Soft Error Protection for Embedded Memories. [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:- [Conf]
- T. Kaya, Isao Shirakawa, Ryusuke Miyamoto, Takao Onoye
Design of Embedded System for Video Coding with Logic-Enhanced DRAM and Configurable Process. [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:- [Conf]
- Philippe Magarshack
SoC's Trends and Challenges going to 0.10µm. [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:- [Conf]
- M. Templeton
Challenges and Opportunities Created by the SoC Shockwave. [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:- [Conf]
- Alvin Jee
Defect-Oriented Analysis of Memory BIST Tests. [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:7-11 [Conf]
- Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda
A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques. [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:12-16 [Conf]
- Farzin Karimi, Fabrizio Lombardi
A Scan-Bist Environment for Testing Embedded Memories. [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:17-0 [Conf]
- Daniele Rossi, Cecilia Metra, Bruno Riccò
Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories. [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:27-31 [Conf]
- Bernard Coloma, Patrick Delaunay, Olivier Husson
High Speed 15 ns 4 Mbits SRAM for Space Application. [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:32-38 [Conf]
- D. Bied-Charreton, D. Guillon, B. Jacques
The YATE Fail-Safe Interface: The User's Point of View. [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:39-43 [Conf]
- Alberto Manzone, Diego De Costantini
Fault Tolerant Insertion and Verification: A Case Study. [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:44-48 [Conf]
- Luca Schiano, Cecilia Metra, Diego Marino
Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems. [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:49-56 [Conf]
- Emmanuel Rondey, Yann Tellier, Simone Borri
A Silicon-Based Yield Gain Evaluation Methodology for Embedded-SRAMs with Different Redundancy Scenarios. [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:57-61 [Conf]
- Valery A. Vardanian, Yervant Zorian
A March-Based Fault Location Algorithm for Static Random Access Memories. [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:62-67 [Conf]
- Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu
A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories. [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:68-0 [Conf]
- Robert Gibbins, R. Dean Adams, Thomas J. Eckenrode, Michael Ouellette, Yuejian Wu
Design and Test of a 9-port SRAM for a 100Gb/s STS-1 Switch. [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:83-0 [Conf]
- Masashi Hashimoto
Adder Merged DRAM Architecture. [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:88-94 [Conf]
- Said Hamdioui, A. J. van de Goor, Mike Rodgers
March SS: A Test for All Static Simple RAM Faults. [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:95-100 [Conf]
- Farzin Karimi, Fred J. Meyer, Fabrizio Lombardi
Random Testing of Multi-Port Static Random Access Memories. [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:101-108 [Conf]
- Raja Venkatesh, Sailesh Kumar, Joji Philip, Sunil Shukla
A Fault Modeling Technique to Test Memory BIST Algorithms. [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:109-116 [Conf]
- Michael Redeker, Bruce F. Cockburn, Duncan G. Elliott, Yunan Xiang, Sue Ann Ung
Fault Modeling and Pattern-Sensitivity Testing for a Multilevel DRAM. [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:117-122 [Conf]
- Michael Redeker, Bruce F. Cockburn, Duncan G. Elliott
An Investigation into Crosstalk Noise in DRAM Structures. [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:123-0 [Conf]
- Jean Michel Portal, L. Forli, H. Aziza, Didier Née
An Automated Design Methodology for EEPROM Cell (ADE). [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:137-142 [Conf]
- Cyrille Dray, Philippe Gendrier
A Novel Memory Array Based on an Annular Single-Poly EPROM Cell for Use in Standard CMOS Technology. [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:143-148 [Conf]
- Caroline Papaix, Jean Michel Daga
A New Single Ended Sense Amplifier for Low Voltage Embedded EEPROM Non Volatile Memories. [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:149-156 [Conf]
- T. Devoivre, M. Lunenborg, C. Julien, J.-P. Carrere, P. Ferreira, W. J. Toren, A. VandeGoor, P. Gayet, T. Berger, O. Hinsinger, P. Vannier, Y. Trouiller, Y. Rody, P.-J. Goirand, R. Palla, I. Thomas, F. Guyader, D. Roy, B. Borot, N. Planes, S. Naudet, F. Pico, D. Duca, F. Lalanne, D. Heslinga, M. Haond
Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC). [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:157-162 [Conf]
- Mario R. Casu, Philippe Flatresse
Converting an Embedded Low-Power SRAM from Bulk to PD-SOI. [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:163-167 [Conf]
- R. Laffont, J. Razafindramora, P. Canet, R. Bouchakour, J. M. Mirabel
Decreasing EEPROM Programming Bias With Negative Voltage, Reliability Impact. [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:168-176 [Conf]
- Bruce F. Cockburn
Panel on Advanced Embedded Memory Technologies. [Citation Graph (0, 0)][DBLP]
MTDT, 2002, pp:177-178 [Conf]
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