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Conferences in DBLP

Memory Technology, Design and Testing (mtdt)
2003 (conf/mtdt/2003)

  1. Betty Prince
    Application Specific DRAMs Today. [Citation Graph (0, 0)][DBLP]
    MTDT, 2003, pp:7-13 [Conf]
  2. Bruce F. Cockburn, Jesús Hernández Tapia, Duncan G. Elliott
    A Multilevel DRAM with Hierarchical Bitlines and Serial Sensing. [Citation Graph (0, 0)][DBLP]
    MTDT, 2003, pp:14-19 [Conf]
  3. Youhei Zenda, Koji Nakamae, Hiromu Fujioka
    Cost Optimum Embedded DRAM Design by Yield Analysis. [Citation Graph (0, 0)][DBLP]
    MTDT, 2003, pp:20-0 [Conf]
  4. Zaid Al-Ars, A. J. van de Goor
    Systematic Memory Test Generation for DRAM Defects Causing Two Floating Nodes. [Citation Graph (0, 0)][DBLP]
    MTDT, 2003, pp:27-32 [Conf]
  5. Zaid Al-Ars, Said Hamdioui, A. J. van de Goor
    A Fault Primitive Based Analysis of Linked Faults in RAMs. [Citation Graph (0, 0)][DBLP]
    MTDT, 2003, pp:33-0 [Conf]
  6. Jörg E. Vollrath
    Output Timing Measurement Using an Idd Method. [Citation Graph (0, 0)][DBLP]
    MTDT, 2003, pp:43-46 [Conf]
  7. Baosheng Wang, Josh Yang, André Ivanov
    Reducing Test Time of Embedded SRAMs. [Citation Graph (0, 0)][DBLP]
    MTDT, 2003, pp:47-52 [Conf]
  8. Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu Li
    A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories. [Citation Graph (0, 0)][DBLP]
    MTDT, 2003, pp:53-0 [Conf]
  9. Roger Barth
    ITRS Commodity Memory Roadmap. [Citation Graph (0, 0)][DBLP]
    MTDT, 2003, pp:61-63 [Conf]
  10. Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri
    Optimal Spare Utilization in Repairable and Reliable Memory Cores. [Citation Graph (0, 0)][DBLP]
    MTDT, 2003, pp:64-71 [Conf]
  11. Robert C. Aitken
    Applying Defect-Based Test to Embedded Memories in a COT Model. [Citation Graph (0, 0)][DBLP]
    MTDT, 2003, pp:72-0 [Conf]
  12. Jean Michel Daga, Caroline Papaix, Emmanuel Racape, Marylene Combe, Vincent Sialelli, Jeanine Guichaoua
    A 40ns Random Access Time Low Voltage 2Mbits EEPROM Memory for Embedded Applications. [Citation Graph (0, 0)][DBLP]
    MTDT, 2003, pp:81-85 [Conf]
  13. Daniel Salamon, Bruce F. Cockburn
    An Electrical Simulation Model for the Chalcogenide Phase-Change Memory Cell. [Citation Graph (0, 0)][DBLP]
    MTDT, 2003, pp:86-0 [Conf]
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NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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