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Conferences in DBLP

Workshop on Microprocessor Test and Verification (mtv)
2003 (conf/mtv/2003)

  1. Allon Adir, Roy Emek, Yoav Katz, Anatoly Koyfman
    DeepTrans - A Model-based Approach to Functional Verification of Address Translation Mechanisms. [Citation Graph (0, 0)][DBLP]
    MTV, 2003, pp:3-6 [Conf]
  2. Mrinal Bose, Mark H. Nodine, William R. Jurasz Jr., Vlad Zavadsky, Arvind Chodavadia, Lincoln R. Nunes
    Modeling IP Responses in Testcase Generation for Systems-on-Chip Verification. [Citation Graph (0, 0)][DBLP]
    MTV, 2003, pp:7-10 [Conf]
  3. F. Hunsinger, Sebastien Francois, Ahmed Amine Jerraya
    Definition of a systematic method for the generation of software test programs allowing the functional verification of System On Chip (SoC). [Citation Graph (0, 0)][DBLP]
    MTV, 2003, pp:11-0 [Conf]
  4. Wangqi Qiu, D. M. H. Walker
    Testing the Path Delay Faults of ISCAS85 Circuit c6288. [Citation Graph (0, 0)][DBLP]
    MTV, 2003, pp:19-0 [Conf]
  5. V. V. Iyer
    Comparison of Verification Methodologies for Datapath Testing. [Citation Graph (0, 0)][DBLP]
    MTV, 2003, pp:27-31 [Conf]
  6. Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir
    A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits. [Citation Graph (0, 0)][DBLP]
    MTV, 2003, pp:32-37 [Conf]
  7. Elham Safi, Zohreh Karimi, Maghsoud Abbaspour, Zainalabedin Navabi
    Utilizing Various ADL Facets for Instruction Level CPU Test. [Citation Graph (0, 0)][DBLP]
    MTV, 2003, pp:38-0 [Conf]
  8. Alexander Klaiber, Sinclair Chau
    Automatic Detection of Logic Bugs in Hardware Designs. [Citation Graph (0, 0)][DBLP]
    MTV, 2003, pp:47-53 [Conf]
  9. Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris
    Extraction Error Analysis, Diagnosis and Correction in Custom-Made High-Performance Designs. [Citation Graph (0, 0)][DBLP]
    MTV, 2003, pp:54-59 [Conf]
  10. Andreas G. Veneris
    Fault Diagnosis and Logic Debugging Using Boolean Satisfiability. [Citation Graph (0, 0)][DBLP]
    MTV, 2003, pp:60-0 [Conf]
  11. Ateet Bhalla, Inês Lynce, José T. de Sousa, João P. Marques Silva
    Heuristic Backtracking Algorithms for SAT. [Citation Graph (0, 0)][DBLP]
    MTV, 2003, pp:69-74 [Conf]
  12. Ohad Shacham, Emmanuel Zarpas
    Tuning the VSIDS Decision Heuristic for Bounded Model Checking. [Citation Graph (0, 0)][DBLP]
    MTV, 2003, pp:75-0 [Conf]
  13. Prabhat Mishra, Nikil D. Dutt
    A Methodology for Validation of Microprocessors using Equivalence Checking. [Citation Graph (0, 0)][DBLP]
    MTV, 2003, pp:83-88 [Conf]
  14. Alessandro Fin, Franco Fummi, Massimo Poncino, Graziano Pravadelli
    A SystemC-based Framework for Properties Incompleteness Evaluation. [Citation Graph (0, 0)][DBLP]
    MTV, 2003, pp:89-94 [Conf]
  15. Mahesh A. Iyer
    A Robust and Scalable Technique for the Constraints Solving Problem in High-Level Verification. [Citation Graph (0, 0)][DBLP]
    MTV, 2003, pp:95-0 [Conf]
  16. Joan Oliver, Octavian D. Mocanu, Carles Ferrer
    Energy Awareness through Software Optimisation as a Performance Estimate Case Study of the MC68HC908GP32 Microcontroller. [Citation Graph (0, 0)][DBLP]
    MTV, 2003, pp:111-0 [Conf]
  17. Matthew W. Heath, Ian G. Harris
    A Deterministic Globally Asynchronous Locally Synchronousy Microprocessor Architecture. [Citation Graph (0, 0)][DBLP]
    MTV, 2003, pp:119-0 [Conf]
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002