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Conferences in DBLP

Workshop on Microprocessor Test and Verification (mtv)
2004 (conf/mtv/2004)


  1. Preface. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:- [Conf]

  2. Program Committee. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:- [Conf]

  3. Workshop Organizing Committee. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:- [Conf]

  4. Acknowledgement. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:- [Conf]
  5. Anshuman S. Nadkarni, Tom Kenville
    TiGeR, the Transmeta Instruction GEneratoR: A Production Based, Pseudo Random Instruction x86 Test Generator. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:2-7 [Conf]
  6. W. Lindsay, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero
    Automatic Test Programs Generation Driven by Internal Performance Counters. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:8-13 [Conf]
  7. Arkan Abdulrahman, Spyros Tragoudas
    Compact ATPG for Concurrent SOC Testing. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:16-21 [Conf]
  8. Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda
    Using Infrastructure IPs to Support SW-Based Self-Test of Processor Cores. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:22-27 [Conf]
  9. Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner
    Extreme Formal Modeling (XFM) for Hardware Models. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:30-35 [Conf]
  10. Xiuli Sun, Jinzhao Wu, Xiaoyu Song, Mila E. Majster-Cederbaum
    Formal Specification of an Asynchronous Processor via Action Refinement. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:36-41 [Conf]
  11. Moayad Fahim Ali, Andreas G. Veneris, Sean Safarpour, Magdy S. Abadir, Freescale Semiconductor, Rolf Drechsler, Alexander Smith
    Debugging Sequential Circuits Using Boolean Satisfiability. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:44-49 [Conf]
  12. Marc Herbstritt, Thomas Kmieciak, Bernd Becker
    On the Impact of Structural Circuit Partitioning on SAT-Based Combinational Circuit Verification. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:50-55 [Conf]
  13. Tobias Schubert, Bernd Becker
    PICHAFF2 - A Hierarchical Parallel SAT Solver. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:56-61 [Conf]
  14. Mark Litterick, Joachim Geishauser
    Robust Vera Coding Techniques for Gate-Level and Tester-Compliant SoC Verification Environments. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:64-78 [Conf]
  15. Prabhat Mishra, Nikil D. Dutt, Yaron Kashai
    Functional Verification of Pipelined Processors: A Case Study. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:79-84 [Conf]
  16. Michele Borgatti, Andrea Fedeli, Umberto Rossi, Jean-Luc Lambert, Imed Moussa, Franco Fummi, Cristina Marconcini, Graziano Pravadelli
    A Verification Methodology for Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:85-90 [Conf]
  17. M. Moiz Khan, Spyros Tragoudas, Magdy S. Abadir, Jiang Brandon Liu
    Identification of Gates for Covering all Critical Paths. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:92-96 [Conf]
  18. Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
    A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:97-102 [Conf]
  19. Jing Zeng, Magdy S. Abadir, G. Vandling, Li-C. Wang, S. Karako, Jacob A. Abraham
    On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:103-109 [Conf]
  20. Eyal Bin, Laurent Fournier
    Micro-Architecture Verification for Microprocessors. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:112-113 [Conf]
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