Conferences in DBLP
Preface. [Citation Graph (0, 0)][DBLP ] Conf ] Program Committee. [Citation Graph (0, 0)][DBLP ] Conf ] Workshop Organizing Committee. [Citation Graph (0, 0)][DBLP ] Conf ] Acknowledgement. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Qin , Sharad Malik A Study of Architecture Description Languages from a Model-based Perspective. [Citation Graph (0, 0)][DBLP ] Conf ] Brian Kahne , Aseem Gupta , Peter Wilson , Nikil D. Dutt An Introduction to the Plasma Language. [Citation Graph (0, 0)][DBLP ] Conf ] Marc Herbstritt , Bernd Becker On SAT-based Bounded Invariant Checking of Blackbox Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Tobias Schubert , Matthew D. T. Lewis , Bernd Becker PaMira - A Parallel SAT Solver with Knowledge Sharing. [Citation Graph (0, 0)][DBLP ] Conf ] Paolo Bernardi , Ernesto Sánchez , Massimiliano Schillaci , Matteo Sonza Reorda , Giovanni Squillero Diagnosing Faulty Functional Units in Processors by Using Automatically Generated Test Sets. [Citation Graph (0, 0)][DBLP ] Conf ] Moayad Fahim Ali , Sean Safarpour , Andreas G. Veneris , Magdy S. Abadir , Rolf Drechsler Post-Verification Debugging of Hierarchical Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Jennifer Dworak An Investigation of Excitation Balance and Additional Mandatory Conditions for the Diagnosis of Fortuitously Detected Defects. [Citation Graph (0, 0)][DBLP ] Conf ] Paolo Bernardi , Michelangelo Grosso , Maurizio Rebaudengo , Matteo Sonza Reorda Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Bin Xue , D. M. H. Walker Is IDDQ Test of Microprocessors Feasible? [Citation Graph (0, 0)][DBLP ] Conf ] Giuseppe Di Guglielmo , Franco Fummi , Cristina Marconcini , Graziano Pravadelli A Pseudo-Deterministic Functional ATPG based on EFSM Traversing. [Citation Graph (0, 0)][DBLP ] Conf ] Charles H.-P. Wen , Li-C. Wang Simulation Data Mining for Functional Test Pattern Justification. [Citation Graph (0, 0)][DBLP ] Conf ] Jorge Campos , Hussain Al-Asaad Search-Space Optimizations for High-Level ATPG. [Citation Graph (0, 0)][DBLP ] Conf ] John Mark Nolen , Rabi N. Mahapatra A TDM Test Scheduling Method for Network-on-Chip Systems. [Citation Graph (0, 0)][DBLP ] Conf ] David Berner , Hiren D. Patel , Deepak Mathaikutty , Sandeep K. Shukla Automated Extraction of Structural Information from SystemC-based IP for Validation. [Citation Graph (0, 0)][DBLP ] Conf ] Soohong P. Kim Pre-Silicon Validation of IPF Memory Ordering for Multi-Core Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Jayanta Bhadra , Magdy S. Abadir , David Burgess , Ekaterina Trofimova Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Prabhat Mishra , Heon-Mo Koo , Zhuo Huang Language-driven Validation of Pipelined Processors using Satisfiability Solvers. [Citation Graph (0, 0)][DBLP ] Conf ] Nicola Bombieri , Andrea Fedeli , Franco Fummi On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Große , Ulrich Kühne , Rolf Drechsler HW/SW Co-Verification of a RISC CPU using Bounded Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Brian Kahne , Magdy S. Abadir Retiming Verification Using Sequential Equivalence Checking. [Citation Graph (0, 0)][DBLP ] Conf ] 