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Conferences in DBLP

Workshop on Microprocessor Test and Verification (mtv)
2006 (conf/mtv/2006)


  1. Program Committee. [Citation Graph (0, 0)][DBLP]
    MTV, 2006, pp:- [Conf]

  2. Workshop Organizing Committee. [Citation Graph (0, 0)][DBLP]
    MTV, 2006, pp:- [Conf]

  3. Acknowledgement. [Citation Graph (0, 0)][DBLP]
    MTV, 2006, pp:- [Conf]

  4. Preface. [Citation Graph (0, 0)][DBLP]
    MTV, 2006, pp:- [Conf]
  5. Paolo Bernardi, Leticia Maria Veiras Bolzani, Alberto Manzone, Marcella Guagliumi Massimo Osella, Massimo Violante, Matteo Sonza Reorda
    Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications. [Citation Graph (0, 0)][DBLP]
    MTV, 2006, pp:3-8 [Conf]
  6. Jorge Campos, Hussain Al-Asaad
    Circuit Profiling Mechanisms for High-Level {ATPG}. [Citation Graph (0, 0)][DBLP]
    MTV, 2006, pp:9-14 [Conf]
  7. Vijay Gangaram, Deepa Bhan, James K. Caldwell
    Functional Test Selection for High Volume Manufacturing. [Citation Graph (0, 0)][DBLP]
    MTV, 2006, pp:15-19 [Conf]
  8. Jozsef Sziray
    Test Calculation for Logic and Delay Faults in Digital Circuits. [Citation Graph (0, 0)][DBLP]
    MTV, 2006, pp:20-32 [Conf]
  9. Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra, Magdy S. Abadir
    Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study. [Citation Graph (0, 0)][DBLP]
    MTV, 2006, pp:33-36 [Conf]
  10. Marc Herbstritt, Bernd Becker, Christoph Scholl
    Advanced SAT-Techniques for Bounded Model Checking of Blackbox Designs. [Citation Graph (0, 0)][DBLP]
    MTV, 2006, pp:37-44 [Conf]
  11. Tamarah Arons, Elad Elster, Terry Murphy, Eli Singerman
    Embedded Software Validation: Applying Formal Techniques for Coverage and Test Generation. [Citation Graph (0, 0)][DBLP]
    MTV, 2006, pp:45-51 [Conf]
  12. Noah Bamford, Rekha Bangalore, Eric Chapman, Hector Chavez, Rajeev Dasari, Yinfang Lin, Edgar Jimenez
    Challenges in System on Chip Verification. [Citation Graph (0, 0)][DBLP]
    MTV, 2006, pp:52-60 [Conf]
  13. Hassan Al-Sukhni, David Lindberg, James Holt, Michele Reese
    Workload Slicing for Characterizing New Features in High Performance Microprocessors. [Citation Graph (0, 0)][DBLP]
    MTV, 2006, pp:61-67 [Conf]
  14. Hiren D. Patel, Sandeep K. Shukla
    Deep vs. Shallow, Kernel vs. Language--What is Better for Heterogeneous Modeling in {SystemC}?. [Citation Graph (0, 0)][DBLP]
    MTV, 2006, pp:68-75 [Conf]
  15. Hyun Sung Kim, D. M. H. Walker
    Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in {VLSI} Circuits. [Citation Graph (0, 0)][DBLP]
    MTV, 2006, pp:76-82 [Conf]
  16. Jianmin Zhang, Ming Yan, Sikun Li
    Debug Support for Scalable System-on-Chip. [Citation Graph (0, 0)][DBLP]
    MTV, 2006, pp:83-87 [Conf]
  17. Sean Safarpour, Andreas G. Veneris
    Abstraction and Refinement Techniques in Automated Design Debugging. [Citation Graph (0, 0)][DBLP]
    MTV, 2006, pp:88-93 [Conf]
  18. Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Tayung Liu, Yu-Chin Hsu
    Diagnosing Silicon Failures Based on Functional Test Patterns. [Citation Graph (0, 0)][DBLP]
    MTV, 2006, pp:94-98 [Conf]
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