Conferences in DBLP
Thomas Illgen , Stefan Ortmann Challenges and Trends in the Engineering of Automatic Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Philipp Limbourg , Hans-Dieter Kochs Predicting Imprecise Failure Rates from Similar Components: A Case Study Using Neural Networks and Gaussian Procedures. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Galke , René Kothe , Heinrich Theodor Vierhaus Logic Self Repair. [Citation Graph (0, 0)][DBLP ] Conf ] Bernhard Fechner Microcode with Embedded Timing Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Jörg Keller , Johannes Magauer Error-Correcting Codes in Steganography. [Citation Graph (0, 0)][DBLP ] Conf ] Zinaida Benenson , Felix C. Freiling , Thorsten Holz , Dogan Kesdogan , Lucia Draque Penso Safety, Liveness, and Information Flow: Dependability Revisited. [Citation Graph (0, 0)][DBLP ] Conf ] Péter Domokos , István Majzik Automated Construction of Dependability Models by Aspect-Oriented Modeling and Model Transformation. [Citation Graph (0, 0)][DBLP ] Conf ] Grzegorz Lukawski , Krzysztof Sapiecha Software Functional Fault Injector for SDDS. [Citation Graph (0, 0)][DBLP ] Conf ] Dawid Trawczynski , Janusz Sosnowski , Janusz Zalewski Dependability Evaluation of Real-Time Network Interfaces. [Citation Graph (0, 0)][DBLP ] Conf ] Astrit Ademaj , Hermann Kopetz , Petr Grillinger , Klaus Steinhammer , Alexander Hanzlik Fault-Tolerant Time-Triggered Ethernet Configuration with Star Topology. [Citation Graph (0, 0)][DBLP ] Conf ] Spiro Trikaliotis , Jörg Diederich 0002 Utilizing a Fault-Tolerance Protocol for Colocating Interfering Cells in a Wireless Network. [Citation Graph (0, 0)][DBLP ] Conf ] Yankin Tanurhan IP security and future of reconfigurability in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Christopher Claus , Florian Helmut Müller , Walter Stechele Combitgen: A new approach for creating partial bitstreams in Virtex-II Pro. [Citation Graph (0, 0)][DBLP ] Conf ] Markus Rullmann , Renate Merker Design and Implementation of Reconfigurable Tasks with Minimum Reconfiguration Overhead. [Citation Graph (0, 0)][DBLP ] Conf ] Steffen Köhler , Martin Zimmerling , Martin Zabel , Rainer G. Spallek Prototyping and Application Development Framework for Dynamically Reconfigurable DSP Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Heiko Hinkelmann , Peter Zipf , Manfred Glesner A metric for the energy-efficiency of dynamically reconfigurable systems. [Citation Graph (0, 0)][DBLP ] Conf ] Stefan Döbrich , Christian Hochberger Predicting Hardware Acceleration Through Object Caching in AMIDAR Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Udo Kebschull Applications of FPGA Reconfiguration for Experiments in High Energy Physics. [Citation Graph (0, 0)][DBLP ] Conf ] Shannon Koh , Oliver Diessel COMMA: A Communications Methodology for Dynamic Module-based Reconfiguration of FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Mateusz Majer , Ali Ahmadinia , Christophe Bobda , Jürgen Teich A Flexible Reconfiguration Manager for the Erlangen Slot Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Florian Dittmann , Tales Heimfarth Clock Frequency Variation of Partially Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Neil W. Bergmann , John A. Williams , Jie Han , Yi Chen A Process Model for Hardware Modules in Reconfigurable System-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Ghaffari Fakhreddine , Michel Auguin An efficient on-line Approach for on-chip HW/SW partitioner and scheduler. [Citation Graph (0, 0)][DBLP ] Conf ] Reiner W. Hartenstein From Organic Computing to Reconfigurable Supercomputing. [Citation Graph (0, 0)][DBLP ] Conf ] Jürgen Becker , Kurt Brändle , Uwe Brinkschulte , Jörg Henkel , Wolfgang Karl , Thorsten Köster , Michael Wenz , Heinz Wörn Digital On-Demand Computing Organism for Real-Time Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Döring Levels in Configurability for CRC Calculation. [Citation Graph (0, 0)][DBLP ] Conf ] Francisco Fons , Mariano Fons , Enrique Cantó , Mariano López Dynamically Reconfigurable CORDIC Coprocessor for Trigonometric. [Citation Graph (0, 0)][DBLP ] Conf ] Felix Wolf , Felix Freitag , Bernd Mohr , Shirley Moore , Brian J. N. Wylie Large Event Traces in Parallel Performance Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Hubert Eichner , Carsten Trinitis , Tobias Klug Software Shared Memory Communications with InfiniBand. [Citation Graph (0, 0)][DBLP ] Conf ] Stefano Belforte , Matthew Norman , Subir Sarkar , Igor Sfiligoi , Douglas Thain , Frank Wuerthwein Using Condor Glide-Ins and Parrot to Move from Dedicated Ressources to the Grid. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Bader , Miriam Mehl , Christoph Zenger Stack-oriented memory allocation using space filling curves for parallel PDE-solvers. [Citation Graph (0, 0)][DBLP ] Conf ] Jan Treibig , Silke Berler , Ulrich Rüde ORCAN: A platform for complex parallel simulation software. [Citation Graph (0, 0)][DBLP ] Conf ] Christof Meigen , Jörg Keller A simple parallel algorithm for the stepwise approximate computation of Voronoi diagrams of line segments. [Citation Graph (0, 0)][DBLP ] Conf ] Mattias Eriksson , Christoph W. Keßler , Mikhail Chalabine Load balancing of irregular parallel divide-and-conquer algorithms in group-SPMD programming environments. [Citation Graph (0, 0)][DBLP ] Conf ] Mathias Halbach , Rolf Hoffmann Minimising the Hardware Resources for a Cellular Automaton with Moving Creatures. [Citation Graph (0, 0)][DBLP ] Conf ] Di Wu , Tiejun Hu , Dake Liu A Single Issue DSP based Multi-standard Media Processor for Mobile Platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Torsten Hoefler , Torsten Mehlan , Frank Mietke , Wolfgang Rehm Adding Low-Cost Hardware Barrier Support to Small Commodity Clusters. [Citation Graph (0, 0)][DBLP ] Conf ] Jie Tao , Wolfgang Karl Performance Evaluation of Adaptive Caching Schemes. [Citation Graph (0, 0)][DBLP ] Conf ] 