Conferences in DBLP

Power-Aware Computer Systems (PACS) (pacs)
2000 (conf/pacs/2000)

1. Flavius Gruian
   System-Level Design Methods for Low-Energy Architectures Containing Variable Voltage Processors. [Citation Graph (0, 0)][DBLP]
   PACS, 2000, pp:1-12 [Conf]
   
2. Zhenyu Tang, Norman Chang, Shen Lin, Weize Xie, O. Sam Nakagawa, Lei He
   Ramp Up/Down Functional Unit to Reduce Step Power. [Citation Graph (0, 0)][DBLP]
   PACS, 2000, pp:13-24 [Conf]
   
3. Alper Buyuktosunoglu, Stanley Schuster, David Brooks, Pradip Bose, Peter W. Cook, David H. Albonesi
   An Adaptive Issue Queue for Reduced Power at High Performance. [Citation Graph (0, 0)][DBLP]
   PACS, 2000, pp:25-39 [Conf]
   
4. Paul Marchal, Chun Wong, Aggeliki Prayati, Nathalie Cossement, Francky Catthoor, Rudy Lauwereins, Diederik Verkest, Hugo De Man
   Dynamic Memory Oriented Transformations in the MPEG4 IM1-Player on a Low Power Platform. [Citation Graph (0, 0)][DBLP]
   PACS, 2000, pp:40-50 [Conf]
   
5. Jeongseon Euh, Wayne Burleson
   Exploiting Content Variation and Perception in Power-Aware 3D Graphics Rendering. [Citation Graph (0, 0)][DBLP]
   PACS, 2000, pp:51-64 [Conf]
   
6. Chung-Hsing Hsu, Ulrich Kremer, Michael S. Hsiao
   Compiler-Directed Dynamic Frequency and Voltage Scheduling. [Citation Graph (0, 0)][DBLP]
   PACS, 2000, pp:65-81 [Conf]
   
7. Stefanos Kaxiras, Zhigang Hu, Girija J. Narlikar, Rae McLellan
   Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power. [Citation Graph (0, 0)][DBLP]
   PACS, 2000, pp:82-96 [Conf]
   
8. Roberto Maro, Yu Bai, R. Iris Bahar
   Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors. [Citation Graph (0, 0)][DBLP]
   PACS, 2000, pp:97-111 [Conf]
   
9. Ashutosh S. Dhodapkar, Chee How Lim, George Cai, W. Robert Daasch
   TEM²P²EST: A Thermal Enabled Multi-model Power/Performance ESTimator. [Citation Graph (0, 0)][DBLP]
   PACS, 2000, pp:112-125 [Conf]
   
10. David Brooks, Margaret Martonosi, John-David Wellman, Pradip Bose
    Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor. [Citation Graph (0, 0)][DBLP]
    PACS, 2000, pp:126-136 [Conf]
    
11. Soraya Ghiasi, Dirk Grunwald
    A Comparison of Two Architectural Power Models. [Citation Graph (0, 0)][DBLP]
    PACS, 2000, pp:137-152 [Conf]