Conferences in DBLP
Hartmut Schmeck Organic Computing-Vision and Challenge for System Design. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Blaszczyk The Role of Parallel Computing at ABB Corporate Research Switzerland. [Citation Graph (0, 0)][DBLP ] Conf ] Carsten Clauss , Martin Pöppe , Thomas Bemmerl Optimising MPI Applications for Heterogeneous Coupled Clusters with MetaMPICH. [Citation Graph (0, 0)][DBLP ] Conf ] Georgios Tsilikas , Martin Fleury Matrix Multiplication Performance on Commodity Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Adam Smyk , Marek Tudruj Parallel Implementation of FDTD Computations Based on Macro Data Flow Paradigm. [Citation Graph (0, 0)][DBLP ] Conf ] Henryk Krawczyk , Tomasz Madajczak Optimal Programming of Critical Sections in Modern Network Processors under Performance Requirements. [Citation Graph (0, 0)][DBLP ] Conf ] Dirk Fimmel , Stefan Quitzk , Wolfgang Schwarz Large-Scale Tolerance Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Jie Guo , Michael Hosemann , Gerhard Fettweis Employing Compilers for Determining Architectural Features of Application-Specific DSPs. [Citation Graph (0, 0)][DBLP ] Conf ] Gordon Cichon , Pablo Robelly , Hendrik Seidel , Marcus Bronzel , Gerhard Fettweis Compiler Scheduling for STA-Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Matolin , Jörg Schreiter , Stefan Getzlaff , René Schüffny An Analog VLSI Pulsed Neural Network Implementation for Image Segmentation. [Citation Graph (0, 0)][DBLP ] Conf ] Lukasz Masko , Grégory Mounié , Denis Trystram , Marek Tudruj Moldable Task Scheduling in Dynamic SMP Clusters with Communication on the Fly. [Citation Graph (0, 0)][DBLP ] Conf ] Lukasz Masko Program Graph Scheduling for SMP Clusters with Communication on-the-Fly Based on Extended DS Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Tomasz Madajczak An Optimal Abstraction Model for Hardware Multithreading in Modern Processor Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Hannig , Jürgen Teich Dynamic Piecewise Linear/Regular Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Sebastian Siegel , Renate Merker Algorithm Partitioning including Optimized Data-Reuse for Processor Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] W. Bielecki , Rafal Kocisz A Modified Vertex Method for Parallelization of Arbitrary Nested Loops. [Citation Graph (0, 0)][DBLP ] Conf ] Stanislaw Chrobot Introducing Variable Sharing to Process Calculi. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Dufour , Jean Bélanger A PC-Based Real-Time Parallel Simulator of Electric Systems and Drives. [Citation Graph (0, 0)][DBLP ] Conf ] Uwe Hatnik , Sven Altmann Using ModelSim, Matlab/Simulink and NS for Simulation of Distributed Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Noboru Tanabe , Hironori Nakajo , Hirotaka Hakozaki , Masasige Nakatake , Yasunori Dohi , Hideharu Amano A New Memory Module for Memory Intensive Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Sauer , Matthias Gries , José Ignacio Gómez , Scott J. Weber , Kurt Keutzer Developing a Flexible Interface for RapidIO, Hypertransport, and PCI-Express. [Citation Graph (0, 0)][DBLP ] Conf ] Rolf Hoffmann , Wolfgang Heenes , Mathias Halbach Implementation of the Massively Parallel Model GCA. [Citation Graph (0, 0)][DBLP ] Conf ] Andrzej Jordan , Pawel B. Myszkowski , Konrad Radzik The Parallel Computations for the Linear State Equations. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Benner , Enrique S. Quintana-Ortí , Gregorio Quintana-Ortí Computing Passive Reduced-Order Models for Circuit Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Wojciech Walendziuk , Andrzej Jordan , Adam Skorek Visualization of the Parallel Finite-Difference Time-Domain Method Computations Results. [Citation Graph (0, 0)][DBLP ] Conf ] Wojciech Bozejko , Mieczyslaw Wodecki Parallel Tabu Search Method Approach for Very Difficult Permutation Scheduling Problems. [Citation Graph (0, 0)][DBLP ] Conf ] Lev Kirischian , Irina Terterian , Pil Woo Chun , Vadim Geurkov Re-Configurable Parallel Stream Processor with Self-Assembling and Self-Restorable Micro-Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Tobias Oppold , Thomas Schweizer , Tommy Kuhn , Wolfgang Rosenstiel A Design Environment for Processor-Like Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Jörg Schneider , Vincent Kotzsch , Steffen Rülke Demonstrator: Reuse Automation for Reconfigurable System-on-Chip Design within a DVB Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Kühn , Sorin A. Huss Dynamically Reconfigurable Hardware for Object-Oriented Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Jaroslaw Forenc , Andrzej Jordan The Modified Speculative Method for the Transient States Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Boguslaw Butrylo , Christian Vollaire , Laurent Nicolas Limits of the Distributed Finite Element Time Domain Algorithm in Multi-Computer Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Przemyslaw Stpiczynski Numerical Evaluation of Linear Recurrences on High Performance Computers and Clusters of Workstations. [Citation Graph (0, 0)][DBLP ] Conf ] Matthias Grünewald , Dinh Khoi Le , Uwe Kastens , Jörg-Christian Niemann , Mario Porrmann , Ulrich Rückert , Adrian Slowik , Michael Thies Network Application Driven Instruction Set Extensions for Embedded Processing Clusters. [Citation Graph (0, 0)][DBLP ] Conf ] Mathias Kortke , Jan Müller , Rainer Schaffer , Sebastian Siegel , Renate Merker , Jürgen Kelber A Parallel Hardware-Software System for Signal Processing Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Hendrik Seidel , Gordon Cichon , Pablo Robelly , Marcus Bronzel , Gerhard Fettweis Hardware / Software Co-Design of a SIMD-DSP-Based DVB-T Receiver. [Citation Graph (0, 0)][DBLP ] Conf ] Carsten Maple , Liang Guo , Jie Zhang Parallel Genetic Algorithms for Third Generation Mobile Network Planning. [Citation Graph (0, 0)][DBLP ] Conf ] Bernhard Fechner , Jörg Keller A Fault-Tolerant Voting Scheme for Multithreaded Environments. [Citation Graph (0, 0)][DBLP ] Conf ] Anna Derezinska Estimating Dependability of Parallel FFT Application using Fault Injection. [Citation Graph (0, 0)][DBLP ] Conf ] Jamil Saif , Henryk Krawczyk Tuning of Parallel ROI Matching Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Dietmar Fey , Lutz Hoppe , Andreas Loos Reconfigurable On-Chip SIMD Processor Architectures for Intelligent CMOS Camera Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Eryk Laskowski Program Scheduling in Look-Ahead Reconfigurable Parallel Systems with Multiple Communication Resources. [Citation Graph (0, 0)][DBLP ] Conf ] V. G. Khoroshevsky Architecture and Functioning of Large-Scale Distributed Reconfigurable Computer Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Claudia Roberta Calidonna , Mario Mango Furnari The Cellular Automata Network Compiler System: Modules and Features. [Citation Graph (0, 0)][DBLP ] Conf ] Torsten Mehlan , Wolfgang Rehm , Ralph Engler , Tobias Wenzel Providing a High-Performance VIA-Module for LAM/MPI. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Buchholz , Andriy Panchenko An EM Algorithm for Fitting of Real Traffic Traces to PH-Distribution. [Citation Graph (0, 0)][DBLP ] Conf ] Silvio Misera , Heinrich Theodor Vierhaus FIT - A Parallel Hierarchical Fault Simulation Environment. [Citation Graph (0, 0)][DBLP ] Conf ] A. S. Nepomniaschaya , Zbigniew Kokosinski Associative Graph Processor and Its Properties. [Citation Graph (0, 0)][DBLP ] Conf ] Grzegorz Pastuszak A Novel Architecture of Arithmetic Coder in JPEG2000 Based on Parallel Symbol Encoding. [Citation Graph (0, 0)][DBLP ] Conf ] Marc Franzmeier , Christopher Pohl , Mario Porrmann , Ulrich Rückert Hardware Accelerated Data Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Axel Siebenborn , Oliver Bringmann , Wolfgang Rosenstiel Communication Analysis for Network-on-Chip Design. [Citation Graph (0, 0)][DBLP ] Conf ] Damian Kopanski , Janusz Borkowski , Marek Tudruj Co-Ordination of Parallel GRID Applications using Synchronizers. [Citation Graph (0, 0)][DBLP ] Conf ] Janusz Borkowski Parallel Program Control Based on Hierarchically Detected Consistent Global States. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Piotr Bycul A Graphical Interface to a Parallel Solver: PSGE Description Through an Application. [Citation Graph (0, 0)][DBLP ] Conf ] Sylvain Alliot , Laurentiu Nicolae , Martijn van Veelen A Tool for Exploring the Large Scale Signal Processing Systems Specification. [Citation Graph (0, 0)][DBLP ] Conf ] Jork Löser , Hermann Härtig Using Switched Ethernet for Hard Real-Time Communication. [Citation Graph (0, 0)][DBLP ] Conf ] A. Rodríguez , A. González , Manuel P. Malumbres Performance Evaluation of Parallel MPEG-4 Video Coding Algorithms on Clusters of Workstations. [Citation Graph (0, 0)][DBLP ] Conf ] Georgios Dimitriou , Constantine D. Polychronopoulos Loop Scheduling for Multithreaded Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Pawel Kaczmarek , Henryk Krawczyk Influence of Exception Handling on Distributed Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Pablo Robelly , Gordon Cichon , Hendrik Seidel , Gerhard Fettweis Automatic Code Generation for SIMD DSP Architectures: An Algebraic Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Erik Vonnahme , Björn Griese , Mario Porrmann , Ulrich Rückert Dynamic Reconfiguration of Real-Time Network Interfaces. [Citation Graph (0, 0)][DBLP ] Conf ] Victor E. Malyshkin , I. Naumkin , N. Malyshkin , Vladimir D. Korneev , Michael Ostapkevich Digital Electromagnetic Model of the Power System: Parallel Implementation for Multicomputers. [Citation Graph (0, 0)][DBLP ] Conf ] Marek Tudruj , Lukasz Masko Fine-Grain Numerical Computations in Dynamic SMP Clusters with Communication on the Fly. [Citation Graph (0, 0)][DBLP ] Conf ] Pawel Czarnul , Arkadiusz Urbaniak , Marcin Fraczak , Maciej Dyczkowski , Bartlomiej Balcerek Towards Easy-to-Use Checkpointing of MPI Applications within CLUSTERIX. [Citation Graph (0, 0)][DBLP ] Conf ] Octav Brudaru , Octavian Buzatu Distributed Genetic Algorithm for Finding Fuzzy Rational Approximators. [Citation Graph (0, 0)][DBLP ] Conf ] Eryk Laskowski , Richard Olejnik , Bernard Toursel , Marek Tudruj Scheduling Byte Code-Defined Data Dependence Graphs of Object Oriented Programs. [Citation Graph (0, 0)][DBLP ] Conf ] 