Conferences in DBLP
Alexey L. Lastovetsky Scientific Programming for Heterogeneous Systems - Bridging the Gap between Algorithms and Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Pawel Gepner , Michal F. Kowalik Multi-Core Processors: New Way to Achieve High System Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Dan Grigoras Challenges to the Design of Mobile Middleware Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Carsten Trinitis Automatic High Voltage Apparatus Optimization: Making it More Engineer-Friendly. [Citation Graph (0, 0)][DBLP ] Conf ] Bernhard Fechner A Fault-Tolerant Dynamic Fetch Policy for SMT Processors in Multi-Bus Environments. [Citation Graph (0, 0)][DBLP ] Conf ] D. Doreen Hephzibah Miriam , T. Srinivasan , R. Deepa An Efficient SRA Based Isomorphic Task Allocation Scheme for k - ary n - cube Massively Parallel Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Marcin Gorawski , Michal Gorawski Balanced Spatio-Temporal Data Warehouse with R-MVB, STCAT and BITMAP Indexes. [Citation Graph (0, 0)][DBLP ] Conf ] Dajin Wang An Algorithm to Embed Hamiltonian Cycles in Crossed Cubes. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Sauer , Matthias Gries , J.-C. Niemann , M. Porrmann , M. Thies Application-Driven Development of Concurrent Packet Processing Platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Tomasz Madajczak , Henryk Krawczyk Integrating SHECS-Based Critical Sections with Hardware SMP Scheduler in TLP-CMPs. [Citation Graph (0, 0)][DBLP ] Conf ] Faezeh Montazeri , Mehdi Salmani Jelodar , S. Najmeh Fakhraie , Seid Mehdi Fakhraie Evolutionary Multiprocessor Task Scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Marek Tudruj , Lukasz Masko Fast Matrix Multiplication in Dynamic SMP Clusters with Communication on the Fly in Systems on Chip Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Adam Smyk , Marek Tudruj , Lukasz Masko Open MP Extension for Multithreaded Computing with Dynamic SMP Processor Clusters with Communication on the Fly. [Citation Graph (0, 0)][DBLP ] Conf ] Jan Müller Generalised Resource Model for Parallel Instruction Scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Lukasz Masko , Gregory Mounie , Denis Trystram , Marek Tudruj Program Graph Structuring for Execution in Dynamic SMP Clusters Using Moldable Tasks. [Citation Graph (0, 0)][DBLP ] Conf ] Abdellah Yousfi , Abdelouafi Meziane The Centisecond Two Levels Hidden Semi Markov Model (CTLHSMM). [Citation Graph (0, 0)][DBLP ] Conf ] Adrian Kosowski , Lukasz Kuszner Energy Optimisation in Resilient Self-Stabilizing Processes. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Kauhaus , Dietmar Fey Building Mini-Grid Environments with Virtual Private Networks: A Pragmatic Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Lamch , Roman Wyrzykowski Specification, Analysis and Testing of Grid Environments Using Abstract State Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Adam Kozakiewicz , Andrzej Karbowski A Two-Level Approach to Building a Campus Grid. [Citation Graph (0, 0)][DBLP ] Conf ] Jirí Jaros , Milos Ohlídal , Václav Dvorák Complexity of Collective Communications on NoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Florin Pop , Ciprian Dobre , Gavril Godza , Valentin Cristea A Simulation Model for Grid Scheduling Analysis and Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] T. Srinivasan , N. Dhanasekar , M. Nivedita , R. Dhivyakrishnan , A. A. Azeezunnisa Scalable and Parallel Aggregated Bit Vector Packet Classification Using Prefix Computation Model. [Citation Graph (0, 0)][DBLP ] Conf ] Stefan Dydel , Krzysztof Benedyczak , Piotr Bala Enabling Reconfigurable Hardware Accelerators for the Grid. [Citation Graph (0, 0)][DBLP ] Conf ] Hritam Dutta , Frank Hannig , Jürgen Teich Hierarchical Partitioning for Piecewise Linear Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] K. Ashwin Kumar , Aasish Kumar Pappu , K. Sarath Kumar , Sudip Sanyal Hybrid Approach for Parallelization of Sequential Code with Function Level and Block Level Parallelization. [Citation Graph (0, 0)][DBLP ] Conf ] Rainer Schaffer , Renate Merker , Francky Catthoor Derivation of Packing Instructions for Exploiting Sub-Word Parallelism. [Citation Graph (0, 0)][DBLP ] Conf ] Sebastian Siegel , Rainer Schaffer , Renate Merker Efficient Realization of the Edge Detection Algorithm on a Processor Array with Parallelism on Two Levels. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander A. Petrovsky , Sergei L. Shkredov Automatic Generation of Split-Radix 2-4 Parallel-Pipeline FFT Processors: Hardware Reconfiguration and Core Optimizations. [Citation Graph (0, 0)][DBLP ] Conf ] Torsten Mehlan , Jochen Strunk , Torsten Hoefler , Frank Mietke , Wolfgang Rehm IRS - A Portable Interface for Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Sarma Nedunuri , John Y. Cheung , Prakasa Nedunuri Design of Low Memory Usage Discrete Wavelet Transform on FPGA Using Novel Diagonal Scan. [Citation Graph (0, 0)][DBLP ] Conf ] A. Pedram , M. R. Jamali , Seid Mehdi Fakhraie , Caro Lucas Reconfigurable Parallel Hardware for Computing Local Linear Neuro-Fuzzy Model. [Citation Graph (0, 0)][DBLP ] Conf ] Eryk Laskowski , Marek Tudruj Efficient Parallel Embedded Computing through Look-Ahead Configured Dynamic Inter-Processor Connections. [Citation Graph (0, 0)][DBLP ] Conf ] Oleg Maslennikow , Anatolij Sergiyenko Mapping DSP Algorithms into FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Björn Griese , Boris Kettelhoit , Mario Porrmann Evaluation of On-Chip Interfaces for Dynamically Reconfigurable Coprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Jacek Pierzchlewski , Pawel Sniatala , Blazej Nowakowski , Andrzej Rybarczyk , Wojciech Wencel FPGA Chip as a System Master for Hardware Aided Parallel Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Torsten Hoefler , Carsten Viertel , Torsten Mehlan , Frank Mietke , Wolfgang Rehm Assessing Single-Message and Multi-Node Communication Performance of InfiniBand. [Citation Graph (0, 0)][DBLP ] Conf ] Janusz Borkowski , Damian Kopanski , Marek Tudruj Parallel Irregular Computations Control Based on Global Predicate Monitoring. [Citation Graph (0, 0)][DBLP ] Conf ] Farshad Safaei , Ahmad Khonsari , Mahmood Fathy , Nasser Alzeidi , Mohamed Ould-Khaoua Performance Modeling of Fault-Tolerant Circuit-Switched Communication Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmed Yassin Al-Dubai , Imed Romdhani A Performance Study of Path Based Multicast Communication Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Risto Honkanen Nearly-All-Optical Routing in Sparse Optical Tori. [Citation Graph (0, 0)][DBLP ] Conf ] Valérie Fiolet , Eryk Laskowski , Richard Olejnik , Lukasz Masko , Bernard Toursel , Marek Tudruj Optimizing Distributed Data Mining Applications Based on Object Clustering Methods. [Citation Graph (0, 0)][DBLP ] Conf ] Changjun Hu , Jing Li , Jue Wang , Yonghong Li , Liang Ding , Jianjiang Li Communication Generation for Irregular Parallel Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Kirill V. Pavsky Stochastic Analysis of Solving Complex Problem on Distributed Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Wojciech Bozejko , Mieczyslaw Wodecki A Fast Parallel Dynasearch Algorithm for Some Scheduling Problems. [Citation Graph (0, 0)][DBLP ] Conf ] S. Viswanadha Raju , A. Vinaya Babu , M. Mrudula Backend Engine for Parallel String Matching Using Boolean Matrix. [Citation Graph (0, 0)][DBLP ] Conf ] Przemyslaw Stpiczynski , Joanna Potiopa Piecewise Cubic Interpolation on Distributed Memory Parallel Computers and Clusters of Workstations. [Citation Graph (0, 0)][DBLP ] Conf ] Suri Pushpa , Prasad Vinod , Carsten Maple Creating a Forest of Binary Search Trees for a Multiprocessor System. [Citation Graph (0, 0)][DBLP ] Conf ] Jaroslaw Forenc Time Domain Decomposition in Parallel Analysis of Transient States. [Citation Graph (0, 0)][DBLP ] Conf ] Andrzej Rybarczyk , Michal Szulc , Jaroslaw Wencel The CCM Based Implementation of the Parallel Variant of BiCG Algorithm Suitable for Massively Parallel Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Grzegorz M. Wojcik , Wieslaw A. Kaminski Pattern Separation in the Model of Mammalian Visual System. [Citation Graph (0, 0)][DBLP ] Conf ] Joanna Kolodziej , Krzysztof Jauernig , Aleksander Cieslar HGSNash Strategy as the Decision-Making Method for Water Resource Systems with External Disagreement of Interests. [Citation Graph (0, 0)][DBLP ] Conf ] Wojciech Kwedlo , Krzysztof Bandurski A Parallel Differential Evolution Algorithm A Parallel Differential Evolution Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Karol Banczyk , Tomasz Boinski , Henryk Krawczyk Parallelisation of Genetic Algorithms for Solving University Timetabling Problems. [Citation Graph (0, 0)][DBLP ] Conf ] Jan Kwiatkowski , Marcin Pawlik , Urszula Markowska-Kaczmar , Dariusz Konieczny Performance Evaluation of Different Kohenen Network Parallelization Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Amin Farmahini Farahani , Mehdi Kamal , Mehdi Salmani Jelodar Parallel-Genetic-Algorithm-Based HW/SW Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] R. Deepa , T. Srinivasan , D. Doreen Hephzibah Miriam An Efficient Task Scheduling Technique in Heterogeneous Systems Using Self-Adaptive Selection-Based Genetic Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Zbigniew J. Czech Speeding Up Sequential Simulated Annealing by Parallelization. [Citation Graph (0, 0)][DBLP ] Conf ] Yunsong Wu , Graham M. Megson Parallel Linear Hashtable Motion Estimation Algorithm for Parallel Video Processing. [Citation Graph (0, 0)][DBLP ] Conf ] A. Rodríguez , A. González , Manuel P. Malumbres Hierarchical Parallelization of an H.264/AVC Video Encoder. [Citation Graph (0, 0)][DBLP ] Conf ] Marcus Komann , Dietmar Fey Marching Pixels - Using Organic Computing Principles in Embedded Parallel Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Schmidt , Andreas Loos , Dietmar Fey A Space-Time Multiplex Architecture for 3D Stacked Embedded Vision Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Grzegorz Pastuszak Parallel Symbol Architectures for H.264/AVC Binary Coder Based on Arithmetic Coding. [Citation Graph (0, 0)][DBLP ] Conf ] Awni Itradat , M. Omair Ahmad , Ali Shatnawi A Delay-Optimal Static Scheduling of DSP Applications Mapped onto Multiprocessor Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] G. Rubin , K. Bielawski , J. Baszun A Hardware Conceptual Prototyping of the Genetic Algorithm to Adaptive IIR Filtering. [Citation Graph (0, 0)][DBLP ] Conf ] Rafal Kapela , Andrzej Rybarczyk The Neighboring Pixel Representation for Efficient Binary Image Processing Operations. [Citation Graph (0, 0)][DBLP ] Conf ] Qi Huang , Kaiyu Qin , Wenyong Wang A Software Architecture Based on Multi-Agent and Grid Computing for Electric Power System Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Qi Huang , Jianbo Yi , Shi Jing , Ke Huang Development of an MPI for Power System Distributed Parallel Computing in Wide Area Network with P2P Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Rajesh K. Bawa , V. Rathish Kumar , Tanu Gupta Parallel Mesh Division Algorithm For General Linear Two Point Boundary Value Problems. [Citation Graph (0, 0)][DBLP ] Conf ] Adam Smyk , Marek Tudruj Parallel FDTD Computations Optimized by Program Macro Data Flow Graph Redeployment. [Citation Graph (0, 0)][DBLP ] Conf ] Leszek Kasprzyk , Ryszard Nawrowski , Andrzej Tomczewski Using a Parallel Virtual Machine to Optimize Lighting Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Qi Huang , Xiaoping Chen , Bingfeng Wang , Ronghai Cai , Kaiyu Qin The Concept of Computing on Chip (CoC) for Electric Power System Application. [Citation Graph (0, 0)][DBLP ] Conf ] Luis García , Coromoto León , Gara Miranda , Casiano Rodríguez Two-Dimensional Cutting Stock Problem: Shared Memory Parallelizations. [Citation Graph (0, 0)][DBLP ] Conf ] Carmen B. Navarrete , Susana Holgado , Eloy Anguiano MPI and Non-MPI Simulations for Epitaxial Surface Growth. [Citation Graph (0, 0)][DBLP ] Conf ] Mariusz Pelc Computer Cluster as a Tool in the Continuous Exact State Reconstruction. [Citation Graph (0, 0)][DBLP ] Conf ] Pawel B. Myszkowski The Change of State Variables in Global Linearization of Non-Linear State Equation. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Piotr Bycul , Pawel B. Myszkowski A Computer Aided Global Linearization of a Non-Linear Electric circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Wojciech Walendziuk , Slawomir Kwieckowski The Use of the Dynamic Space Decomposition Algorithm of a Computational Area in Heterogeneous Cluster Computations. [Citation Graph (0, 0)][DBLP ] Conf ] Boguslaw Butrylo Distributed Optimization of Temperature Field for Reliable Construction of Electronic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] 