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Conferences in DBLP

Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) (patmos)
2000 (conf/patmos/2000)

  1. Rene van Leuken, Reinder Nouta, Alexander de Graaf
    Constraints, Hurdles, and Opportunities for a Successful European Take-Up Action. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:1-2 [Conf]
  2. Manuela Anton, Mauro Chinosi, Daniele Sirtori, Roberto Zafalon
    Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:3-13 [Conf]
  3. Alessandro Bogliolo, Enrico Macii, Virgil Mihailovici, Massimo Poncino
    Power Models for Semi-autonomous RTL Macros. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:14-23 [Conf]
  4. Gerd Jochens, Lars Kruse, Eike Schmidt, Ansgar Stammermann, Wolfgang Nebel
    Power Macro-Modelling for Firm-Macro. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:24-35 [Conf]
  5. Crina Anton, Pierluigi Civera, Ionel Colonescu, Enrico Macii, Massimo Poncino, Alessandro Bogliolo
    RTL Estimation of Steering Logic Power. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:36-46 [Conf]
  6. Nikolaos D. Zervas, S. Theoharis, Athanasios Kakarountas, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis
    Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:47-55 [Conf]
  7. Achim Freimann
    Framework for High-Level Power Estimation of Signal Processing Architectures. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:56-65 [Conf]
  8. Claudia Kretzschmar, Robert Siegmund, Dietmar Müller
    Adaptive Bus Encoding Technique for Switching Activity Reduced Data Transfer over Wide System Buses. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:66-75 [Conf]
  9. George Theodoridis, S. Theoharis, Nikolaos D. Zervas, Constantinos E. Goutis
    Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:76-87 [Conf]
  10. Mary Jane Irwin, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam
    A Holistic Approach to System Level Energy Optimization. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:88-107 [Conf]
  11. Marcello Lajolo, Luciano Lavagno, Matteo Sonza Reorda, Massimo Violante
    Early Power Estimation for System-on-Chip Designs. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:108-117 [Conf]
  12. Reiner W. Hartenstein, Thomas Hoffmann, Ulrich Nageldinger
    Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:118-128 [Conf]
  13. Philippe Maurine, Mustapha Rezzoug, Daniel Auvergne
    Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:129-138 [Conf]
  14. Henrik Eriksson, Per Larsson-Edefors
    Impact of Voltage Scaling on Glitch Power Consumption. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:139-148 [Conf]
  15. Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia
    Degradation Delay Model Extension to CMOS Gates. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:149-158 [Conf]
  16. Mustapha Rezzoug, Philippe Maurine, Daniel Auvergne
    Second Generation Delay Model for Submicron CMOS Process. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:159-167 [Conf]
  17. Nikolai Starodoubtsev, Alexandre V. Bystrov, Alexandre Yakovlev
    Semi-modular Latch Chains for Asynchronous Circuit Design. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:168-177 [Conf]
  18. Francesco Pessolano, Joep L. W. Kessels
    Asynchronous First-in First-out Queues. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:178-186 [Conf]
  19. Athanasios Kakarountas, K. Papadomanolakis, V. Kokkinos, Constantinos E. Goutis
    Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:187-194 [Conf]
  20. Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo
    VLSI Implementation of a Low-Power High-Speed Self-Timed Adder. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:195-204 [Conf]
  21. Holger Sedlak
    Low Power Design Techniques for Contactless Chipcards. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:205-206 [Conf]
  22. Joohee Kim, Marios C. Papaefthymiou
    Dynamic Memory Design for Low Data-Retention Power. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:207-216 [Conf]
  23. Claude Arm, Jean-Marc Masgonty, Christian Piguet
    Double-Latch Clocking Scheme for Low-Power I.P. Cores. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:217-224 [Conf]
  24. Santanu Dutta
    Architecture, Design, and Verification of an 18 Million Transistor Digital Television and Media Processor Chip. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:225-232 [Conf]
  25. Kristof Denolf, Peter Vos, Jan Bormans, Ivo Bolsens
    Cost-Efficient C-Level Design of an MPEG-4 Video Decoder. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:233-242 [Conf]
  26. Dimitrios Soudris, Nikolaos D. Zervas, Antonios Argyriou, Minas Dasygenis, Konstantinos Tatas, Constantinos E. Goutis, Adonios Thanailakis
    Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:243-254 [Conf]
  27. Alexis De Vos, Bart Desoete, A. Adamski, Piotr Pietrzak, M. Sibínski, T. Widerski
    Design of Reversible Logic Circuits by Means of Control Gates. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:255-264 [Conf]
  28. Massimo Alioto, Gaetano Palumbo
    Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:265-275 [Conf]
  29. Christoph Saas, A. Schlaffer, Josef A. Nossek
    An Adiabatic Multiplier. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:276-284 [Conf]
  30. Vassilis Paliouras, Thanos Stouraitis
    Logarithmic Number System for Low-Power Arithmetic. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:285-294 [Conf]
  31. Raúl Jiménez, Antonio J. Acosta, Eduardo J. Peralías, Adoración Rueda
    An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:295-305 [Conf]
  32. Andreas Herrmann, Erich Barke, Mathias Silvant, Jürgen Schlöffel
    PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:306-315 [Conf]
  33. Antonio J. Acosta, Raúl Jiménez, Jorge Juan-Chico, Manuel J. Bellido, Manuel Valencia
    Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:316-326 [Conf]
  34. Tom Wichmann, Manfred Thole
    Computer Aided Generation of Analytic Models for Nonlinear Function Blocks. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:327-335 [Conf]
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