Conferences in DBLP
Hugo De Man Connecting E-Dreams to Deep-Submicron Realities. [Citation Graph (0, 0)][DBLP ] Conf ] Nick Kanopoulos Design Methodology for Rapid Development of SoC ICs Based on an Innovative System Architecture with Emphasis to Timing Closure and Power Consumption Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Kiyoo Itoh , Kenichi Osada , Takayuki Kawahara Low-Voltage Embedded RAMs - Current Status and Future Trends. [Citation Graph (0, 0)][DBLP ] Conf ] Carlo Dallavalle Adaptive Subthreshold Leakage Reduction Through N/P Wells Reverse Biasing. [Citation Graph (0, 0)][DBLP ] Conf ] Domenik Helms , Eike Schmidt , Wolfgang Nebel Leakage in CMOS Circuits - An Introduction. [Citation Graph (0, 0)][DBLP ] Conf ] Hongliang Chang , Haifeng Qian , Sachin S. Sapatnekar The Certainty of Uncertainty: Randomness in Nanometer Design. [Citation Graph (0, 0)][DBLP ] Conf ] Jihong Ren , Mark R. Greenstreet Crosstalk Cancellation for Realistic PCB Buses. [Citation Graph (0, 0)][DBLP ] Conf ] Sabino Salerno , Enrico Macii , Massimo Poncino A Low-Power Encoding Scheme for GigaByte Video Interfaces. [Citation Graph (0, 0)][DBLP ] Conf ] Markus Tahedl , Hans-Jörg Pfleiderer Dynamic Wire Delay and Slew Metrics for Integrated Bus Structures. [Citation Graph (0, 0)][DBLP ] Conf ] Mircea R. Stan , Yan Zhang Perfect 3-Limited-Weight Code for Low Power I/O. [Citation Graph (0, 0)][DBLP ] Conf ] Claudia Kretzschmar , Torsten Bitterlich , Dietmar Müller A High-Level DSM Bus Model for Accurate Exploration of Transmission Behaviour and Power Estimation of Global System Buses. [Citation Graph (0, 0)][DBLP ] Conf ] Xavier Michel , Alexandre Verle , Philippe Maurine , Nadine Azémard , Daniel Auvergne Performance Metric Based Optimization Protocol. [Citation Graph (0, 0)][DBLP ] Conf ] B. Lasbouygues , Robin Wilson , Philippe Maurine , Nadine Azémard , Daniel Auvergne Temperature Dependence in Low Power CMOS UDSM Process. [Citation Graph (0, 0)][DBLP ] Conf ] Mauro Olivieri , Mirko Scarana , Giuseppe Scotti , Alessandro Trifiletti Yield Optimization by Means of Process Parameters Estimation: Comparison Between ABB and ASV Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Nicola Dragone , Michele Quarantelli , Massimo Bertoletti , Carlo Guardiani High Yield Standard Cell Libraries: Optimization and Modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Gabriella Trucco , Giorgio Boselli , Valentino Liberali A Study of Crosstalk Through Bonding and Package Parasitics in CMOS Mixed Analog-Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jun-Cheol Park , Vincent John Mooney III , Philipp Pfeiffenberger Sleepy Stack Reduction of Leakage Power. [Citation Graph (0, 0)][DBLP ] Conf ] Eunseok Song , Young-Kil Park , Soon Kwon , Soo-Ik Chae A Cycle-Accurate Energy Estimator for CMOS Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Schuster , Jean-Luc Nagel , Christian Piguet , Pierre-André Farine Leakage Reduction at the Architectural Level and Its Application to 16 Bit Multiplier Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] André K. Nieuwland , Atul Katoch , Maurice Meijer Reducing Cross-Talk Induced Power Consumption and Delay. [Citation Graph (0, 0)][DBLP ] Conf ] Ilham Hassoune , Amaury Nève , Jean-Didier Legat , Denis Flandre Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell. [Citation Graph (0, 0)][DBLP ] Conf ] Geoff Merrett , Bashir M. Al-Hashimi Leakage Power Analysis and Comparison of Deep Submicron Logic Gates. [Citation Graph (0, 0)][DBLP ] Conf ] Jie Ruan , Mark G. Arnold Threshold Mean Larger Ratio Motion Estimation in MPEG Encoding Using LNS. [Citation Graph (0, 0)][DBLP ] Conf ] Armin Wellig , Julien Zory , Norbert Wehn Energy- and Area-Efficient Deinterleaving Architecture for High-Throughput Wireless Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Matthias Müller , Andreas Wortmann , Dominik Mader , Sven Simon Register Isolation for Synthesizable Register Files. [Citation Graph (0, 0)][DBLP ] Conf ] Carlo Brandolese , William Fornaciari , Fabio Salice Discrete-Event Modeling and Simulation of Superscalar Microprocessor Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Giorgos Dimitrakopoulos , P. Kolovos , P. Kalogerakis , Dimitris Nikolos Design of High-Speed Low-Power Parallel-Prefix VLSI Adders. [Citation Graph (0, 0)][DBLP ] Conf ] Milos Krstic , Eckhard Grass GALSification of IEEE 802.11a Baseband Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Kamel Slimani , Yann Rémond , Gilles Sicard , Marc Renaudin TAST Profiler and Low Energy Asynchronous Design Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] D. J. Kinniment , Alexandre Yakovlev Low Latency Synchronization Through Speculation. [Citation Graph (0, 0)][DBLP ] Conf ] Yijun Liu , Stephen B. Furber Minimizing the Power Consumption of an Asynchronous Multiplier. [Citation Graph (0, 0)][DBLP ] Conf ] Tobias Bjerregaard , Shankar Mahadevan , Jens Sparsø A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Murali Jayapala , Tom Vander Aa , Francisco Barat , Francky Catthoor , Henk Corporaal , Geert Deconinck L0 Cluster Synthesis and Operation Shuffling. [Citation Graph (0, 0)][DBLP ] Conf ] Anders Brødløs Olsen , Finn Büttner , Peter Koch On Combined DVS and Processor Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Christos Drosos , Labros Bisdounis , Dimitris Metafas , Spyros Blionas , Anna Tatsaki A Multi-level Validation Methodology for Wireless Network Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Senn , Johann Laurent , Nathalie Julien , Eric Martin SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level. [Citation Graph (0, 0)][DBLP ] Conf ] Emanuele Lattanzi , Andrea Acquaviva , Alessandro Bogliolo Run-Time Software Monitor of the Power Consumption of Wireless Network Interface Cards. [Citation Graph (0, 0)][DBLP ] Conf ] Meuse N. Oliveira Jr. , Paulo Romero Martins Maciel , Raimundo S. Barreto , Fernando F. Carvalho Towards a Software Power Cost Analysis Framework Using Colored Petri Net. [Citation Graph (0, 0)][DBLP ] Conf ] Francesco Pessolano , R. I. M. P. Meijer A 260ps Quasi-static ALU in 90nm CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Jean Michel Daga , Caroline Papaix , Marylene Combe , Emmanuel Racape , Vincent Sialelli Embedded EEPROM Speed Optimization Using System Power Supply Resources. [Citation Graph (0, 0)][DBLP ] Conf ] Stephan Henzler , Georg Georgakos , Jörg Berthold , Doris Schmitt-Landsiedel Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption. [Citation Graph (0, 0)][DBLP ] Conf ] Uri Frank , Ran Ginosar A Predictive Synchronizer for Periodic Clock Domains. [Citation Graph (0, 0)][DBLP ] Conf ] Jürgen Fischer , Ettore Amirante , Agnese Bargagli-Stoffi , Philip Teichmann , Dominik Gruber , Doris Schmitt-Landsiedel Power Supply Net for Adiabatic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Kazuki Fukuoka , Masaaki Iijima , Kenji Hamada , Masahiro Numa , Akira Tada A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI. [Citation Graph (0, 0)][DBLP ] Conf ] Jingjing Fu , Zuying Luo , Xianlong Hong , Yici Cai , Sheldon X.-D. Tan , Zhu Pan Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery. [Citation Graph (0, 0)][DBLP ] Conf ] Yin Wang , Xianlong Hong , Tong Jing , Yang Yang , Xiaodong Hu , Guiying Yan An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design. [Citation Graph (0, 0)][DBLP ] Conf ] Idris Kaya , Silke Salewski , Markus Olbrich , Erich Barke Wirelength Reduction Using 3-D Physical Design. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel A. Andersson , Lars J. Svensson , Per Larsson-Edefors On Skin Effect in On-Chip Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Delong Shang , Frank P. Burns , Alexandre V. Bystrov , Alexandre V. Koelmans , Danil Sokolov , Alexandre Yakovlev A Low and Balanced Power Implementation of the AES Security Mechanism Using Self-Timed Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Marco Bucci , Michele Guglielmo , Raimondo Luzzi , Alessandro Trifiletti A Power Consumption Randomization Countermeasure for DPA-Resistant Cryptographic Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Ulrich Neffe , Klaus Rothbart , Christian Steger , Reinhold Weiss , Edgar Rieger , Andreas Mühlberger A Flexible and Accurate Energy Model of an Instruction-Set Simulator for Secure Smart Card Software Design. [Citation Graph (0, 0)][DBLP ] Conf ] Athanasios Kakarountas , Vassilis Spiliotopoulos , Spiridon Nikolaidis , Constantinos E. Goutis The Impact of Low-Power Techniques on the Design of Portable Safety-Critical Systems. [Citation Graph (0, 0)][DBLP ] Conf ] David Atienza , Stylianos Mamagkakis , Francky Catthoor , Jose Manuel Mendias , Dimitrios Soudris Modular Construction and Power Modelling of Dynamic Memory Managers for Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Gianluca Palermo , Cristina Silvano PIRATE: A Framework for Power/Performance Exploration of Network-on-Chip Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Anteneh A. Abbo , Richard P. Kleihorst , Vishal Choudhary , Leo Sevat Power Consumption of Performance-Scaled SIMD Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Andrea Bona , Vittorio Zaccaria , Roberto Zafalon Low Effort, High Accuracy Network-on-Chip Power Macro Modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Lap-Fai Leung , Chi-Ying Tsui , Xiaobo Sharon Hu Exploiting Dynamic Workload Variation in Offline Low Energy Voltage Scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Ana Rusu , Alexei Borodenkov , Mohammed Ismail , Hannu Tenhunen Design of a Power/Performance Efficient Single-Loop Sigma-Delta Modulator for Wireless Receivers. [Citation Graph (0, 0)][DBLP ] Conf ] Gustavo Sutter , Jean-Pierre Deschamps , Gery Bioul , Eduardo I. Boemo Power Aware Dividers in FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Zahid Khan , Tughrul Arslan , Ahmet T. Erdogan A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses. [Citation Graph (0, 0)][DBLP ] Conf ] Nikolaos Vassiliadis , A. Chormoviti , Nikolaos Kavvadias , Spiridon Nikolaidis The Effect of Data-Reuse Transformations on Multimedia Applications for Different Processing Platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Patricia Guitton-Ouhamou , Hanene Ben Fradj , Cécile Belleudy , Spiridon Nikolaidis Low Power Co-design Tool and Power Optimization of Schedules and Memory System. [Citation Graph (0, 0)][DBLP ] Conf ] Kostas Masselos , Spyros Blionas , Jean-Yves Mignolet , A. Foster , Dimitrios Soudris , Spiridon Nikolaidis Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform. [Citation Graph (0, 0)][DBLP ] Conf ] Sonia López , Oscar Garnica , José Manuel Colmenar Enhancing GALS Processor Performance Using Data Classification Based on Data Latency. [Citation Graph (0, 0)][DBLP ] Conf ] Nikolaos Kavvadias , Spiridon Nikolaidis Application Analysis with Integrated Identification of Complex Instructions for Configurable Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Amjad Mohsen , Richard Hofmann Power Modeling, Estimation, and Optimization for Automated Co-design of Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Michalis D. Galanis , George Theodoridis , Spyros Tragoudas , Dimitrios Soudris , Constantinos E. Goutis Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path. [Citation Graph (0, 0)][DBLP ] Conf ] Kenny Johansson , Oscar Gustafsson , Lars Wanhammar Power Estimation for Ripple-Carry Adders with Correlated Input Data. [Citation Graph (0, 0)][DBLP ] Conf ] Mark G. Arnold LPVIP: A Low-Power ROM-Less ALU for Low-Precision LNS. [Citation Graph (0, 0)][DBLP ] Conf ] Leonardo Valencia Low Level Adaptive Frequency in Synthesis of High Speed Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Myeong-Hoon Oh , Dong-Soo Har A Novel Mechanism for Delay-Insensitive Data Transfer Based on Current-Mode Multiple Valued Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Jing-ling Yang , Oliver Chiu-sing Choy , Cheong-fat Chan , Kong-Pong Pun Pipelines in Dynamic Dual-Rail Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ali Manzak , Chaitali Chakrabarti Optimum Buffer Size for Dynamic Voltage Processors. [Citation Graph (0, 0)][DBLP ] Conf ] A. Landrault , Nadine Azémard , Philippe Maurine , Michel Robert , Daniel Auvergne Design Optimization with Automated Cell Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Fabricio B. Bastian , Cristiano Lazzari , José Luís Almada Güntzel , Ricardo Reis A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitris Karatasos , Athanasios Kakarountas , George Theodoridis , Constantinos E. Goutis A Novel Constant-Time Fault-Secure Binary Counter. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitrios Velenis , Eby G. Friedman Buffer Sizing for Crosstalk Induced Delay Uncertainty. [Citation Graph (0, 0)][DBLP ] Conf ] P. Vouzis , Vassilis Paliouras Optimal Logarithmic Representation in Terms of SNR Behavior. [Citation Graph (0, 0)][DBLP ] Conf ] Y. S. Son , J. W. Na A New Logic Transformation Method for Both Low Power and High Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew Kinane , Valentin Muresan , Noel E. O'Connor , Noel Murphy , Seán Marlow Energy-Efficient Hardware Architecture for Variable N-point 1D DCT. [Citation Graph (0, 0)][DBLP ] Conf ] Stephan Henzler , Georg Georgakos , Jörg Berthold , Doris Schmitt-Landsiedel Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Maili , Damian Dalton , Christian Steger A Generic Timing Mechanism for Using the APPLES Gate-Level Simulator in a Mixed-Level Simulation Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Howard Chen , Daniel L. Ostapko Modeling Temporal and Spatial Power Supply Voltage Variation for Timing Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Tudor Murgan , Alberto García Ortiz , Clemens Schlachta , Heiko Zimmer , Mihail Petrov , Manfred Glesner On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Alejandro Millán , Jorge Juan-Chico , Manuel J. Bellido , Paulino Ruiz-de-Clavijo , David Guerrero , Enrique Ostúa Signal Sampling Based Transition Modeling for Digital Gates Characterization. [Citation Graph (0, 0)][DBLP ] Conf ] B. Lasbouygues , Robin Wilson , Philippe Maurine , Nadine Azémard , Daniel Auvergne Physical Extension of the Logical Effort Model. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Caputa , Henrik Fredriksson , Martin Hansson , Stefan Andersson , Atila Alvandpour , Christer Svensson An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Alberto García Ortiz , Tudor Murgan , Manfred Glesner Moment-Based Estimation of Switching Activity for Correlated Distributions. [Citation Graph (0, 0)][DBLP ] Conf ] Minh Quang Do , Per Larsson-Edefors , Lars Bengtsson Table-Based Total Power Consumption Estimation of Memory Arrays for Architects. [Citation Graph (0, 0)][DBLP ] Conf ] Tobias Gemmeke , Tobias G. Noll A Physically Oriented Model to Quantify the Noise-on-Delay Effect. [Citation Graph (0, 0)][DBLP ] Conf ] Stefan Cserveny , Jean-Marc Masgonty , Christian Piguet Noise Margin in Low Power SRAM Cells. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Celinski , Derek Abbott , Sorin Cotofana Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic. [Citation Graph (0, 0)][DBLP ] Conf ] 