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Conferences in DBLP

Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) (patmos)
2003 (conf/patmos/2003)

  1. Andrea Cuomo
    Architectural Challenges for the Next Decade Integrated Platforms. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:1- [Conf]
  2. G. Privitera, Francesco Pessolano
    Analysis of High-Speed Logic Families. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:2-10 [Conf]
  3. Pradeep Varma, Ashutosh Chakraborty
    Low-Voltage, Double-Edge-Triggered Flip Flop. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:11-20 [Conf]
  4. Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
    A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:21-30 [Conf]
  5. Luis Mengibar, Luis Entrena, Michael G. Lorenz, Raul Sánchez-Reillo
    State Encoding for Low-Power FSMs in FPGA. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:31-40 [Conf]
  6. Tim Schoenauer, Jörg Berthold, Christoph Heer
    Reduced Leverage of Dual Supply voltages in Ultra Deep Submicron Technologies. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:41-50 [Conf]
  7. José Luis Rosselló, Jaume Segura
    A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:51-59 [Conf]
  8. Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne
    CMOS Gate Sizing under Delay Constraint. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:60-69 [Conf]
  9. E. Seebacher, Gerhard Rappitsch, H. Höller
    Process Characterization for Low VTH and Low Power Design. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:70-79 [Conf]
  10. Josep Rius, Alejandro Peidro, Salvador Manich, Rosa Rodriguez-Sánchez
    Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:80-89 [Conf]
  11. Mario R. Casu, Mariagrazia Graziano, Gianluca Piccinini, Guido Masera, Maurizio Zamboni
    Effects of Temperature in Deep-Submicron Global Interconnect Optimization. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:90-100 [Conf]
  12. Jérôme Lescot, François J. R. Clément
    Interconnect Parasitic Extraction Tool for Radio-Frequency Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:101-110 [Conf]
  13. Sampo Tuuna, Jouni Isoaho
    Estimation of Crosstalk Noise for On-Chip Buses. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:111-120 [Conf]
  14. M. Addino, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
    A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:121-130 [Conf]
  15. Ansgar Stammermann, Domenik Helms, Milan Schulte, Arne Schulz, Wolfgang Nebel
    Interconnect Driven Low Power High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:131-140 [Conf]
  16. Joep L. W. Kessels, Ad M. G. Peeters, Suk-Jin Kim
    Bridging Clock Domains by Synchronizing the Mice in the Mousetrap. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:141-150 [Conf]
  17. Sonia López, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, Román Hermida
    Power-Consumption RRRRreduction in Asynchronous Circuits Using Delay Path Unequalization. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:151-160 [Conf]
  18. Milos Krstic, Eckhard Grass
    New GALS Technique for Datapath Architectures. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:161-170 [Conf]
  19. João Leonardo Fragoso, Gilles Sicard, Marc Renaudin
    Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:171-180 [Conf]
  20. Philippe Maurine, Jean-Baptiste Rigaud, G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin
    Statistic Implementation of QDI Asynchronous Primitives. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:181-191 [Conf]
  21. Antun Domic
    The Emergency of Design for Energy Efficiency: An EDA Perspective. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:192- [Conf]
  22. Jean Oudinot
    The Most Complete Mixed-Signal Simulation Solution with ADVance MS. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:193- [Conf]
  23. Louis Scheffer
    Signal Integrity and Power Supply Network Analysis of Deep SubMicron Chips. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:194- [Conf]

  24. Power Management in Synopsys Galaxy Design Platform. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:195- [Conf]

  25. Open Multimedia Platform for Next-Generation Mobile Devices. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:196- [Conf]
  26. B. Arts, N. van der Eng, Marc J. M. Heijligers, H. Munk, Frans Theeuwen, Luca Benini, Enrico Macii, A. Milia, Roberto Maro, A. Bellu
    Statistical Power Estimation of Behavioral Descriptions. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:197-207 [Conf]
  27. Maurizio Bruno, Alberto Macii, Massimo Poncino
    A Statistic Power Model for Non-synthetic RTL Operators. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:208-218 [Conf]
  28. Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad Ghose
    Energy Efficient Register Renaming. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:219-228 [Conf]
  29. S. Cservany, Jean-Marc Masgonty, Christian Piguet
    Stand-by Power Reduction for Storage Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:229-238 [Conf]
  30. José L. Ayala, Marisa Luisa López-Vallejo
    A Unified Framework for Power-Aware Design of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:239-248 [Conf]
  31. Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria
    A Flexible Framework for Fast Multi-objective Design Space Exploration of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:249-258 [Conf]
  32. Fei Li, Lei He, Joseph M. Basile, Rakesh Patel, Hema Ramamurthy
    High Level Area and Current Estimation. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:259-268 [Conf]
  33. Alberto García Ortiz, Lukusa D. Kabulepa, Manfred Glesner
    Switching Activity Estimation in Non-linear Architectures. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:269-278 [Conf]
  34. Spiridon Nikolaidis, Nikolaos Kavvadias, T. Laopoulos, Labros Bisdounis, Spyros Blionas
    Instruction Level Energy Modeling for Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:279-288 [Conf]
  35. Marc Leeman, David Atienza, Francky Catthoor, Vincenzo De Florio, Geert Deconinck, Jose Manuel Mendias, Rudy Lauwereins
    Power Estimation Approach of Dynamic Data Storage on a Hardware Software Boundary Level. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:289-298 [Conf]
  36. Vineela Manne, Akhilesh Tyagi
    An Adiabatic Charge Pump Based Charge Recycling Design Style. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:299-308 [Conf]
  37. Jürgen Fischer, Ettore Amirante, Francesco Randazzo, Giuseppe Iannaccone, Doris Schmitt-Landsiedel
    Reduction of the Energy Consumption in Adiabatic Gates by Optimal Transistor Sizing. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:309-318 [Conf]
  38. Tae-Chan Kim, Meejoung Kim, Chulwoo Kim, Bong-Young Chung, Soo-Won Kim
    Low Power Response Time Accelerator with Full Resolution for LCD Panel. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:319-327 [Conf]
  39. V. Ferentinos, M. Milia, Gauthier Lafruit, Jan Bormans, Francky Catthoor
    Memory Compaction and Power Optimization for Wavelet-Based Coders. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:328-337 [Conf]
  40. Emil Hjalmarson, Robert Hägglund, Lars Wanhammar
    Design Space Exploration and Trade-Offs in Analog Amplifier Design. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:338-347 [Conf]
  41. Ricardo Augusto da Luz Reis
    Power and Timing Driven Physical Design Automation. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:348-357 [Conf]
  42. Ramesh Karri, Piyush Mishra
    Analysis of Energy Consumed by Secure Session Negotiation Protocols in Wireless Networks. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:358-368 [Conf]
  43. Andrea Acquaviva, Tajana Simunic, Vinay Deolalikar, Sumit Roy
    Remote Power Control of Wireless Network Interfaces. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:369-378 [Conf]
  44. Frank Gilbert, Norbert Wehn
    Architecture-Driven Voltage Scaling for High-Throughput Turbo-Decoders. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:379-388 [Conf]
  45. Seyed Reza Abdollahi, B. Bakkaloglu, S. K. Hosseini
    A Fully Digital Numerical-Controlled-Oscillator. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:389-398 [Conf]
  46. Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija
    Energy Optimization of High-Performance Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:399-408 [Conf]
  47. Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Henk Corporaal, Francky Catthoor
    Instruction Buffering Exploration for Low Energy Embedded Processors. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:409-419 [Conf]
  48. Amirali Baniasadi
    Power-Aware Branch Predictor Update for High-Performance Processors. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:420-429 [Conf]
  49. Konstantinos Tatas, K. Siozios, Dimitrios Soudris, Adonios Thanailakis, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas
    Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:430-439 [Conf]
  50. Massimo Ravasi, Marco Mattavelli, Paul R. Schumacher, Robert D. Turney
    High-Level Algorithmic Complexity Analysis for the Implementation of a Motion-JPEG2000 Encoder. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:440-450 [Conf]
  51. Xavier Michel, Alexandre Verle, Nadine Azémard, Philippe Maurine, Daniel Auvergne
    Metric Definition for Circuit Speed Optimization. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:451-460 [Conf]
  52. Grzegorz Tosik, Frédéric Gaffiot, Zbigniew Lisik, Ian O'Connor, Faress Tissafi-Drissi
    Optical versus Electrical Interconnections for Clock Distribution Networks in New VLSI Technologies. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:461-470 [Conf]
  53. Bahman Javadi, Mohsen Naderi, Hossein Pedram, Ali Afzali-Kusha, Mohammad K. Akbari
    An Asynchronous Viterbi Decoder for Low-Power Applications. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:471-480 [Conf]
  54. Eugeni Isern, Miquel Roca, Francesc Moll
    Analysis of the Contribution of Interconnect Effects in the Energy Dissipation of VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:481-490 [Conf]
  55. Raúl Jiménez, Pilar Parra, Pedro Sanmartín, Antonio J. Acosta
    A New Hybrid CBL-CMOS Cell for Optimum Noise/Power Application. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:491-500 [Conf]
  56. David Guerrero, Gustavo Wilke, José Luís Almada Güntzel, Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Alejandro Millán
    Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:501-510 [Conf]
  57. Dongsheng Wang, Peter Suaris, Nan-Chi Chou
    A Practical ASIC Methdology for Flexible Clock Tree Synthesis with Routing Blockages. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:511-519 [Conf]
  58. Byung-Soo Choi, Dong-Ik Lee
    Frequent Value Cache for Low-Power Asynchronous Dual-Rail Bus. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:520-529 [Conf]
  59. Akihito Sakanaka, Toshinori Sato
    Reducing Static Energy of Cache Memories via Prediction-Table-Less Way Prediction. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:530-539 [Conf]
  60. Andrea Acquaviva, Alessandro Bogliolo
    A Bottom-Up Approach to On-Chip Signal Integrity. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:540-549 [Conf]
  61. Wen-Tsong Shiue, Weetit Wanalertlak
    Advanced Cell Modeling Techniques Based on Polynomial Expressions. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:550-558 [Conf]
  62. Paul Flugger
    RTL-Based Signal Statistics Calculation Facilitates Low Power Design Approaches. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:559-568 [Conf]
  63. Anatoly Prihozhy, Marco Mattavelli, Daniel Mlynek
    Data Dependences Critical Path Evaluation at C/C++ System Level Description. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:569-579 [Conf]
  64. Javier Resano, Daniel Mozos, Elena Pérez-Miñana, Hortensia Mecha, Julio Septién
    A Hardware/Software Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance Requirements. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:580-589 [Conf]
  65. Chee Lee, Wen-Tsong Shiue
    Consideration of Control System and Memory Contributions in Practical Resource-Constrained Scheduling for Low Power. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:590-598 [Conf]
  66. Tae-Chan Kim, Chulwoo Kim, Bong-Young Chung, Soo-Won Kim
    Low Power Cache with Successive Tag Comparison Algorithm. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:599-606 [Conf]
  67. Konstantinos Tatas, K. Siozios, Nikolaos Vassiliadis, D. J. Soudris, Spiridon Nikolaidis, S. Siskos, Adonios Thanailakis
    FPGA Architecture Design and Toolset for Logic Implementation. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:607-616 [Conf]
  68. María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida
    Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:617-627 [Conf]
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