Conferences in DBLP
Anatoly Prihozhy , Daniel Mlynek Design of Parallel Implementations by Means of Abstract Dynamic Critical Path Based Profiling of Complex Sequential Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Daniele Paolo Scarpazza , Praveen Raghavan , David Novo , Francky Catthoor , Diederik Verkest Software Simultaneous Multi-Threading, a Technique to Exploit Task-Level Parallelism to Improve Instruction- and Data-Level Parallelism. [Citation Graph (0, 0)][DBLP ] Conf ] Vasily G. Moshnyaga , Hoa Vo , Glenn Reinman , Miodrag Potkonjak Handheld System Energy Reduction by OS-Driven Refresh. [Citation Graph (0, 0)][DBLP ] Conf ] Sriram Sambamurthy , Jacob A. Abraham , Raghuram S. Tupuri Delay Constrained Register Transfer Level Dynamic Power Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Xiao Yan Yu , Robert K. Montoye , Kevin J. Nowka , Bart R. Zeydel , Vojin G. Oklobdzija Circuit Design Style for Energy Efficiency: LSDL and Compound Domino. [Citation Graph (0, 0)][DBLP ] Conf ] Domenik Helms , Marko Hoyer , Wolfgang Nebel Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction Leakage. [Citation Graph (0, 0)][DBLP ] Conf ] José Luis Rosselló , Carol de Benito , Sebastià A. Bota , Jaume Segura Leakage Power Characterization Considering Process Variations. [Citation Graph (0, 0)][DBLP ] Conf ] A. G. Silva-Filho , F. R. Cordeiro , Remy Eskinazi Sant'Anna , Manoel Eusebio de Lima Heuristic for Two-Level Cache Hierarchy Exploration Considering Energy Consumption and Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Hanene Ben Fradj , Cécile Belleudy , Michel Auguin System Level Multi-bank Main Memory Configuration for Energy Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Ka-Ming Keung , Akhilesh Tyagi SRAM CP: A Charge Recycling Design Schema for SRAM. [Citation Graph (0, 0)][DBLP ] Conf ] David Atienza , Praveen Raghavan , José L. Ayala , Giovanni De Micheli , Francky Catthoor , Diederik Verkest , Marisa López-Vallejo Compiler-Driven Leakage Energy Reduction in Banked Register Files. [Citation Graph (0, 0)][DBLP ] Conf ] M. Hillers , W. Nebel Impact of Array Data Flow Analysis on the Design of Energy-Efficient Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Bart R. Zeydel , Vojin G. Oklobdzija Methodology for Energy-Efficient Digital Circuit Sizing: Important Issues and Design Limitations. [Citation Graph (0, 0)][DBLP ] Conf ] Stefan Cserveny Low-Power Adaptive Bias Amplifier for a Large Supply-Range Linear Voltage Regulator. [Citation Graph (0, 0)][DBLP ] Conf ] Milena Vratonjic , Bart R. Zeydel , Vojin G. Oklobdzija Circuit Sizing and Supply-Voltage Selection for Low-Power Digital Circuit Design. [Citation Graph (0, 0)][DBLP ] Conf ] Philippe Grosse , Yves Durand , Paul Feautrier Power Modeling of a NoC Based Design for High Speed Telecommunication Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Tudor Murgan , P. B. Bacinschi , Alberto García Ortiz , Manfred Glesner Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-wire Capacitance. [Citation Graph (0, 0)][DBLP ] Conf ] Kenichi Okada , Takumi Uezono , Kazuya Masu Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology. [Citation Graph (0, 0)][DBLP ] Conf ] A. Sheibanyrad , Alain Greiner Two Efficient Synchronous Û Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Theodoros Giannopoulos , Vassilis Paliouras Low-Power Maximum Magnitude Computation for PAPR Reduction in OFDM Transmitters. [Citation Graph (0, 0)][DBLP ] Conf ] Ashutosh Chakraborty , K. Duraisami , Ashoka Visweswara Sathanur , Prassanna Sithambaram , Alberto Macii , Enrico Macii , Massimo Poncino Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective. [Citation Graph (0, 0)][DBLP ] Conf ] Toshiro Akino , Takashi Hamahata A Clock Generator Driven by a Unified-CBiCMOS Buffer Driver for High Speed and Low Energy Operation. [Citation Graph (0, 0)][DBLP ] Conf ] B. Chung , J. B. Kuo Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Tiago Dias , Nuno Roma , Leonel Sousa Low Power Distance Measurement Unit for Real-Time Hardware Motion Estimators. [Citation Graph (0, 0)][DBLP ] Conf ] Gurhan Kucuk , Can Basaran Reducing Energy Dissipation of Wireless Sensor Processors Using Silent-Store-Filtering MoteCache. [Citation Graph (0, 0)][DBLP ] Conf ] Reouven Elbaz , Lionel Torres , Gilles Sassatelli , Pierre Guillemin , Michel Bardouillet , Albert Martinez A Comparison of Two Approaches Providing Data Encryption and Authentication on a Processor Memory Bus. [Citation Graph (0, 0)][DBLP ] Conf ] Julien Mercier , Christian Dufaza , Mathieu Lisart Methodology for Dynamic Power Verification of Contactless Smartcards. [Citation Graph (0, 0)][DBLP ] Conf ] Jong-Pil Son , Kyu-young Kim , Ji-Yong Jeong , Yogendera Kumar , Soo-Won Kim New Battery Status Checking Method for Implantable Biomedical Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Lima Ferrão , Ricardo Reis , José Luís Almada Güntzel Considering Zero-Arrival Time and Block-Arrival Time in Hierarchical Functional Timing Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Andrea Pugliese 0002 , Gregorio Cappuccino , Giuseppe Cocorullo A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Christophe Alexandre , Marek Sroka , Hugo Clément , Christian Masson Zephyr: A Static Timing Analyzer Integrated in a Trans-hierarchical Refinement Design Flow. [Citation Graph (0, 0)][DBLP ] Conf ] Mini Nanua , David Blaauw Receiver Modeling for Static Functional Crosstalk Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Ajoy Kumar Palit , Kishore K. Duganapalli , Walter Anheier Modeling of Crosstalk Fault in Defective Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Ji-Yong Jeong , Gil-Su Kim , Jong-Pil Son , Woo-Jin Rim , Soo-Won Kim Body Bias Generator for Leakage Power Reduction of Low-Voltage Digital Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Christophe Giacomotto , Nikola Nedovic , Vojin G. Oklobdzija Energy-Delay Space Analysis for Clocked Storage Elements Under Process Variations. [Citation Graph (0, 0)][DBLP ] Conf ] Hai Lin , Yu Wang , Rong Luo , Huazhong Yang , Hui Wang IR-drop Reduction Through Combinational Circuit Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Jianping Hu , Hong Li , Yangbo Wu Low-Power Register File Based on Adiabatic Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Masayuki Kitamura , Masaaki Iijima , Kenji Hamada , Masahiro Numa , Hiromi Notani , Akira Tada , Shigeto Maegawa High Performance CMOS Circuit by Using Charge Recycling Active Body-Bias Controlled SOI. [Citation Graph (0, 0)][DBLP ] Conf ] Kostas Siozios , Dimitrios Soudris , Antonios Thanailakis Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources. [Citation Graph (0, 0)][DBLP ] Conf ] David Elléouet , Yannig Savary , Nathalie Julien An FPGA Power Aware Design Flow. [Citation Graph (0, 0)][DBLP ] Conf ] Yijun Liu , Steve Furber , Zhenkun Li The Design of a Dataflow Coprocessor for Low Power Embedded Hierarchical Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Raúl Jiménez , Pilar Parra , Javier Castro , Manuel Sánchez , Antonio J. Acosta Optimization of Master-Slave Flip-Flops for High-Performance Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Benjamin Nicolle , William Tatinian , Jean Oudinot , Gilles Jacquemod Hierarchical Modeling of a Fractional Phase Locked Loop. [Citation Graph (0, 0)][DBLP ] Conf ] Régis Roubadia , Sami Ajram , Guy Cathébras Low Power and Low Jitter Wideband Clock Synthesizers in CMOS ASICs. [Citation Graph (0, 0)][DBLP ] Conf ] V. Migairou , Robin Wilson , S. Engels , Nadine Azémard , Philippe Maurine Statistical Characterization of Library Timing Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Oguz Ergin Exploiting Narrow Values for Energy Efficiency in the Register Files of Superscalar Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Saihua Lin , Hongli Gao , Huazhong Yang Low Clock Swing D Flip-Flops Design by Using Output Control and MTCMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Jürgen Rauscher , Hans-Jörg Pfleiderer Sensitivity of a Power Supply Damping Method to Resistance and Current Waveform Variations. [Citation Graph (0, 0)][DBLP ] Conf ] Saihua Lin , Huazhong Yang Worst Case Crosstalk Noise Effect Analysis in DSM Circuits by ABCD Modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Guadalupe Miñana , José Ignacio Hidalgo , Oscar Garnica , Juan Lanchares , José Manuel Colmenar , Sonia López A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Andrea Pugliese 0002 , Gregorio Cappuccino , Giuseppe Cocorullo Correct Modelling of Nested Miller Compensated Amplifier for Discrete-Time Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Davide Pandini , Guido A. Repetto Spectral Analysis of the On-Chip Waveforms to Generate Guidelines for EMC-Aware Design. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Tsan Hsieh , Chi-Chia Yu , Chien-Nan Jimmy Liu , Yi-Fang Chiu A Scalable Power Modeling Approach for Embedded Memory Using LIB Format. [Citation Graph (0, 0)][DBLP ] Conf ] Toshinori Sato , Yuu Tanaka , Hidenori Sato , Toshimasa Funaki , Takenori Koushiro , Akihiro Chiyonobu Improving Energy Efficiency Via Speculative Multithreading on MultiCore Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Clemens Schlachta , Manfred Glesner A CMOS Compatible Charge Recovery Logic Family for Low Supply Voltages. [Citation Graph (0, 0)][DBLP ] Conf ] Diganchal Chakraborty , P. P. Chakrabarti , Arijit Mondal , Pallab Dasgupta A Framework for Estimating Peak Power in Gate-Level Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Eslam Yahya , Marc Renaudin QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Massimo Alioto , Massimo Poli , Santina Rocchi , Valerio Vignoli Power Modeling of Precharged Address Bus and Application to Multi-bit DPA Attacks to DES Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] José Carlos S. Palma , Leandro Soares Indrusiak , Fernando Gehm Moraes , Alberto García Ortiz , Manfred Glesner , Ricardo A. L. Reis Adaptive Coding in Networks-on-Chip: Transition Activity Reduction Versus Power Overhead of the Codec Circuitry. [Citation Graph (0, 0)][DBLP ] Conf ] Preetham Lakshmikanthan , Adrian Nunez A Novel Methodology to Reduce Leakage Power in CMOS Complementary Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Massimo Alioto , Massimo Poli , Santina Rocchi , Valerio Vignoli Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Alin Razafindraibe , Michel Robert , Philippe Maurine Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks. [Citation Graph (0, 0)][DBLP ] Conf ] Felipe Machado , Teresa Riesgo , Yago Torroja A Method for Switching Activity Analysis of VHDL-RTL Combinatorial Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Giovanni De Micheli Nanoelectronics: Challenges and Opportunities. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Piguet , Christian Schuster , Jean-Luc Nagel Static and Dynamic Power Reduction by Architecture Selection. [Citation Graph (0, 0)][DBLP ] Conf ] Peter A. Beerel Asynchronous Design for High-Speed and Low-Power Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Robin Wilson Design for Volume Manufacturing in the Deep Submicron ERA. [Citation Graph (0, 0)][DBLP ] Conf ] Francesco Pessolano The Holy Grail of Holistic Low-Power Design. [Citation Graph (0, 0)][DBLP ] Conf ] Jean Oudinot Top Verification of Low Power System with "Checkerboard" Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Francois Thomas The Power Forward Initiative. [Citation Graph (0, 0)][DBLP ] Conf ] 