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Conferences in DBLP

Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) (patmos)
2005 (conf/patmos/2005)

  1. Fernando Castro, Daniel Chaver, Luis Piñuel, Manuel Prieto, Michael C. Huang, Francisco Tirado
    A Power-Efficient and Scalable Load-Store Queue Design. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:1-9 [Conf]
  2. David Rios-Arambula, Aurélien Buhrig, Marc Renaudin
    Power Consumption Reduction Using Dynamic Control of Micro Processor Performance. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:10-18 [Conf]
  3. Philippe Manet, David Bol, Renaud Ambroise, Jean-Didier Legat
    Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:19-29 [Conf]
  4. Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura
    Dynamic Instruction Cascading on GALS Microprocessors. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:30-39 [Conf]
  5. Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar
    Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:40-48 [Conf]
  6. Meuse N. Oliveira Jr., Paulo Romero Martins Maciel, Ricardo Massa Ferreira Lima, Angelo Ribeiro, Cesar Oliveira, Adilson Arcoverde, Raimundo S. Barreto, Eduardo Tavares, Leornado Amorim
    A Retargetable Environment for Power-Aware Code Evaluation: An Approach Based on Coloured Petri Net. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:49-58 [Conf]
  7. Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis
    Designing Low-Power Embedded Software for Mass-Produced Microprocessor by Using a Loop Table in On-Chip Memory. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:59-68 [Conf]
  8. José Manuel Velasco, David Atienza, Katzalin Olcoz, Francky Catthoor, Francisco Tirado, Jose Manuel Mendias
    Energy Characterization of Garbage Collectors for Dynamic Applications on Embedded Systems. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:69-78 [Conf]
  9. Huizhan Yi, Xuejun Yang
    Optimizing the Configuration of Dynamic Voltage Scaling Points in Real-Time Applications. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:79-88 [Conf]
  10. Martin Palkovic, Erik Brockmeyer, Peter Vanbroekhoven, Henk Corporaal, Francky Catthoor
    Systematic Preprocessing of Data Dependent Constructs for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:89-98 [Conf]
  11. Ali Manzak
    Temperature Aware Datapath Scheduling. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:99-106 [Conf]
  12. Bert Geelen, Gauthier Lafruit, V. Ferentinos, Rudy Lauwereins, Diederik Verkest
    Memory Hierarchy Energy Cost of a Direct Filtering Implementation of the Wavelet Transform. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:107-116 [Conf]
  13. Minas Dasygenis, Erik Brockmeyer, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis
    Improving the Memory Bandwidth Utilization Using Loop Transformations. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:117-126 [Conf]
  14. Amjad Mohsen, Richard Hofmann
    Power-Aware Scheduling for Hard Real-Time Embedded Systems Using Voltage-Scaling Enabled Architectures. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:127-136 [Conf]
  15. Mustafa Aktan, Günhan Dündar
    Design of Digital Filters for Low Power Applications Using Integer Quadratic Programming. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:137-145 [Conf]
  16. Arne Schulz, Andreas Schallenberg, Domenik Helms, Milan Schulte, Axel Reimer, Wolfgang Nebel
    A High Level Constant Coefficient Multiplier Power Model for Power Estimation on High Levels of Abstraction. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:146-155 [Conf]
  17. Hyun-Ho Kim, Jung Hee Kim, Yong-hyeog Kang, Young Ik Eom
    An Energy-Tree Based Routing Algorithm in Wireless Ad-Hoc Network Environments. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:156-165 [Conf]
  18. Labros Bisdounis, Spyros Blionas, Enrico Macii, Spiridon Nikolaidis, Roberto Zafalon
    Energy-Aware System-on-Chip for 5 GHz Wireless LANs. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:166-176 [Conf]
  19. Theodoros Giannopoulos, Vassilis Paliouras
    Low-Power VLSI Architectures for OFDM Transmitters Based on PAPR Reduction. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:177-186 [Conf]
  20. Josep Rius, José Pineda de Gyvez, Maurice Meijer
    An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:187-196 [Conf]
  21. Jean-Félix Perotto, Stefan Cserveny
    Power Management for Low-Power Battery Operated Portable Systems Using Current-Mode Techniques. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:197-206 [Conf]
  22. Alexis De Vos, Yvan Van Rentergem
    Power Consumption in Reversible Logic Addressed by a Ramp Voltage. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:207-216 [Conf]
  23. Yuanlin Lu, Vishwani D. Agrawal
    Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for Vth Assignment and Path Balancing. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:217-226 [Conf]
  24. Pankaj Golani, Peter A. Beerel
    Back Annotation in High Speed Asynchronous Design. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:227-236 [Conf]
  25. Tajana Simunic, Kresimir Mihic, Giovanni De Micheli
    Optimization of Reliability and Power Consumption in Systems on a Chip. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:237-246 [Conf]
  26. Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis
    Performance Gains from Partitioning Embedded Applications in Processor-FPGA SoCs. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:247-256 [Conf]
  27. Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong
    A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:257-266 [Conf]
  28. Mariagrazia Graziano, Cristiano Forzan, Davide Pandini
    Power Supply Selective Mapping for Accurate Timing Analysis. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:267-276 [Conf]
  29. Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen
    Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:277-285 [Conf]
  30. Crescenzo D'Alessandro, Delong Shang, Alexandre V. Bystrov, Alexandre Yakovlev
    PSK Signalling on NoC Buses. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:286-296 [Conf]
  31. Ashutosh Chakraborty, Enrico Macii, Massimo Poncino
    Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:297-307 [Conf]
  32. Giorgos Dimitrakopoulos, Dimitris Nikolos
    Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:308-317 [Conf]
  33. Jin Shi, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan
    Efficient Simulation of Power/Ground Networks with Package and Vias. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:318-328 [Conf]
  34. Gregorio Cappuccino, Andrea Pugliese 0002, Giuseppe Cocorullo
    Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:329-336 [Conf]
  35. Alejandro Millán Calderón, Manuel Jesús Bellido Díaz, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, J. Viejo
    Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:337-347 [Conf]
  36. José Luis Rosselló, Sebastià A. Bota, Jaume Segura
    Compact Static Power Model of Complex CMOS Gates. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:348-354 [Conf]
  37. Massimo Alioto, Gaetano Palumbo, Massimo Poli
    Energy Consumption in RC Tree Circuits with Exponential Inputs: An Analytical Model. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:355-363 [Conf]
  38. Yaping Zhan, Andrzej J. Strojwas, Mahesh Sharma, David Newmark
    Statistical Critical Path Analysis Considering Correlations. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:364-373 [Conf]
  39. Didier Van Reeth, Georges G. E. Gielen
    A CAD Platform for Sensor Interfaces in Low-Power Applications. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:374-381 [Conf]
  40. Eduardo Tavares, Raimundo S. Barreto, Paulo Romero Martins Maciel, Meuse N. Oliveira Jr., Adilson Arcoverde, Gabriel Alves, Ricardo Massa Ferreira Lima, Leonardo Barros, Arthur Bessa
    An Integrated Environment for Embedded Hard Real-Time Systems Scheduling with Timing and Energy Constraints. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:382-392 [Conf]
  41. Miodrag Vujkovic, David Wadkins, Carl Sechen
    Efficient Post-layout Power-Delay Curve Generation. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:393-403 [Conf]
  42. Radu Zlatanovici, Borivoje Nikolic
    Power - Performance Optimization for Custom Digital Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:404-414 [Conf]
  43. Siobhán Launders, Colin Doyle, Wesley Cooper
    Switching-Activity Directed Clustering Algorithm for Low Net-Power Implementation of FPGAs. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:415-424 [Conf]
  44. Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán Calderón, David Guerrero Martos, Enrique Ostúa, J. Viejo
    Logic-Level Fast Current Simulation for Digital CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:425-435 [Conf]
  45. Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
    Design of Variable Input Delay Gates for Low Dynamic Power Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:436-445 [Conf]
  46. Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
    Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:446-455 [Conf]
  47. Ireneusz Brzozowski, Andrzej Kos
    Power Dissipation Reduction During Synthesis of Two-Level Logic Based on Probability of Input Vectors Changes. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:456-465 [Conf]
  48. Kimish Patel, Luca Benini, Enrico Macii, Massimo Poncino
    Energy-Efficient Value-Based Selective Refresh for Embedded DRAMs. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:466-476 [Conf]
  49. Prassanna Sithambaram, Alberto Macii, Enrico Macii
    Design and Implementation of a Memory Generator for Low-Energy Application-Specific Block-Enabled SRAMs. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:477-487 [Conf]
  50. Armin Wellig, Julien Zory
    Static Noise Margin Analysis of Sub-threshold SRAM Cells in Deep Sub-micron Technology. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:488-497 [Conf]
  51. Shadi T. Khasawneh, Kanad Ghose
    An Adaptive Technique for Reducing Leakage and Dynamic Power in Register Files and Reorder Buffers. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:498-507 [Conf]
  52. William R. Roberts, Dimitrios Velenis
    Parameter Variation Effects on Timing Characteristics of High Performance Clocked Registers. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:508-517 [Conf]
  53. Konstantina Karagianni, Vassilis Paliouras
    Low-Power Aspects of Nonlinear Signal Processing. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:518-527 [Conf]
  54. Vasily G. Moshnyaga, Eiji Morikawa
    Reducing Energy Consumption of Computer Display by Camera-Based User Monitoring. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:528-539 [Conf]
  55. Nabil Badereddine, Patrick Girard, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault
    Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:540-549 [Conf]
  56. François Macé, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat
    A Design Methodology for Secured ICs Using Dynamic Current Mode Logic. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:550-560 [Conf]
  57. Miguel Casas-Sanchez, Jose Rizo-Morente, Chris J. Bleakley
    Power Consumption Characterisation of the Texas Instruments TMS320VC5510 DSP. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:561-570 [Conf]
  58. Alin Razafindraibe, Michel Robert, Marc Renaudin, Philippe Maurine
    A Method to Design Compact Dual-rail Asynchronous Primitives. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:571-580 [Conf]
  59. Eckhard Grass, Frank Winkler, Milos Krstic, Alexandra Julius, Christian Stahl, Maxim Piz
    Enhanced GALS Techniques for Datapath Applications. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:581-590 [Conf]
  60. Haralambos Michail, Athanasios Kakarountas, George N. Selimis, Costas E. Goutis
    Optimizing SHA-1 Hash Function for High Throughput with a Partial Unrolling Study. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:591-600 [Conf]
  61. Babak Salamat, Amirali Baniasadi
    Area-Aware Pipeline Gating for Embedded Processors. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:601-608 [Conf]
  62. Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo
    Fast Low-Power 64-Bit Modular Hybrid Adder. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:609-617 [Conf]
  63. Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard
    Speed Indicators for Circuit Optimization. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:618-628 [Conf]
  64. Francisco de Toro, Raúl Jiménez, Manuel Sánchez, Julio Ortega
    Synthesis of Hybrid CBL/CMOS Cell Using Multiobjective Evolutionary Algorithms. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:629-637 [Conf]
  65. Philip Teichmann, Jürgen Fischer, Stephan Henzler, Ettore Amirante, Doris Schmitt-Landsiedel
    Power-Clock Gating in Adiabatic Logic Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:638-646 [Conf]
  66. Yijun Liu, Stephen B. Furber
    The Design of an Asynchronous Carry-Lookahead Adder Based on Data Characteristics. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:647-656 [Conf]
  67. Daniel González, Luis Parrilla, Antonio García, Encarnación Castillo, Antonio Lloris-Ruíz
    Efficient Clock Distribution Scheme for VLSI RNS-Enabled Controllers. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:657-665 [Conf]
  68. Francisco-Javier Veredas, Jordi Carrabina
    Power Dissipation Impact of the Technology Mapping Synthesis on Look-Up Table Architectures. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:666-673 [Conf]
  69. Paul Zuber, Peter Gritzmann, Michael Ritter, Walter Stechele
    The Optimal Wire Order for Low Power CMOS. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:674-683 [Conf]
  70. Bécharia Nadji
    Effect of Post-oxidation Annealing on the Electrical Properties of Anodic Oxidized Films in Pure Water. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:684-692 [Conf]
  71. B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine
    Temperature Dependency in UDSM Process. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:693-703 [Conf]
  72. Howard Chen, Louis Hsu
    Circuit Design Techniques for On-Chip Power Supply Noise Monitoring System. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:704-713 [Conf]
  73. Hamid Reza Sadr M. N
    A Novel Approach to the Design of a Linearized Widely Tunable Very Low Power and Low Noise Differential Transconductor. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:714-723 [Conf]
  74. Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija
    A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:724-732 [Conf]
  75. Wolfgang Nebel, Bärbel Mertsching, Birger Kollmeier
    Digital Hearing Aids: Challenges and Solutions for Ultra Low Power. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:733- [Conf]
  76. Thomas Rohdenburg, Volker Hohmann, Birger Kollmeier
    Tutorial Hearing Aid Algorithms. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:734- [Conf]
  77. Arne Schulz, Wolfgang Nebel
    Optimization of Digital Audio Processing Algorithms Suitable for Hearing Aids. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:735-736 [Conf]
  78. Thomas Eisenbach, Bärbel Mertsching, Nikolaus Voß, Frank Schmidtmeier
    Optimization of Modules for Digital Audio Processing. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:737-746 [Conf]
  79. Jan M. Rabaey
    Traveling the Wild Frontier of Ultra Low-Power Design. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:747- [Conf]
  80. Sung-Bae Park
    DLV (Deep Low Voltage): Circuits and Devices. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:748- [Conf]
  81. Magdy Bayoumi
    Wireless Sensor Networks: A New Life Paradigm. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:749- [Conf]
  82. Odysseas G. Koufopavlou, George N. Selimis, Nicolas Sklavos, Paris Kitsos
    Cryptography: Circuits and Systems Approach. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:750- [Conf]
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