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Conferences in DBLP

Architektur von Rechensystemen (arcs)
2007 (conf/arcs/2007)

  1. Afshin Niktash, Hooman Parizi, Nader Bagherzadeh
    A Reconfigurable Processor for Forward Error Correction. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:1-13 [Conf]
  2. Peter Sobe, Volker Hampel
    FPGA-Accelerated Deletion-Tolerant Coding for Reliable Distributed Storage. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:14-27 [Conf]
  3. Peng Li, Dongsheng Wang, Haixia Wang, Meijuan Lu, Weimin Zheng
    LIRAC: Using Live Range Information to Optimize Memory Access. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:28-42 [Conf]
  4. Xuehai Qian, He Huang, Zhenzhong Duan, Junchao Zhang, Nan Yuan, Yongbin Zhou, Hao Zhang, Huimin Cui, Dongrui Fan
    Optimized Register Renaming Scheme for Stack-Based x86 Operations. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:43-56 [Conf]
  5. Praveen Raghavan, Satyakiran Munaga, Estela Rey Ramos, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest
    A Customized Cross-Bar for Data-Shuffling in Domain-Specific SIMD Processors. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:57-68 [Conf]
  6. Subramanian Ramaswamy, Sudhakar Yalamanchili
    Customized Placement for High Performance Embedded Processor Caches. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:69-82 [Conf]
  7. Jörg-Christian Niemann, Christian Liß, Mario Porrmann, Ulrich Rückert
    A Multiprocessor Cache for Massively Parallel SoC Architectures. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:83-97 [Conf]
  8. Raphaël Chand, Luigi Liquori, Michel Cosnard
    Improving Resource Discovery in the Arigatoni Overlay Network. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:98-111 [Conf]
  9. Tae-Hwan Kim, Won-Kee Hong, Hiecheol Kim
    An Effective Multi-hop Broadcast in Vehicular Ad-Hoc Network. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:112-125 [Conf]
  10. Oliver Buchtala, Bernhard Sick
    Functional Knowledge Exchange Within an Intelligent Distributed System. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:126-141 [Conf]
  11. Till Riedel, Christian Decker, Phillip Scholl, Albert Krohn, Michael Beigl
    Architecture for Collaborative Business Items. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:142-156 [Conf]
  12. Edgar Magaña, Laurent Lefèvre, Joan Serrat
    Autonomic Management Architecture for Flexible Grid Services Deployment Based on Policies. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:157-170 [Conf]
  13. Benjamin Satzger, Andreas Pietzowski, Wolfgang Trumler, Theo Ungerer
    Variations and Evaluations of an Adaptive Accrual Failure Detector to Enable Self-healing Properties in Distributed Systems. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:171-184 [Conf]
  14. Ichiro Satoh
    Self-organizing Software Components in Distributed Systems. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:185-198 [Conf]
  15. Paul Kaufmann, Marco Platzner
    Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:199-208 [Conf]
  16. Moez Mnif, Urban Richter, Jürgen Branke, Hartmut Schmeck, Christian Müller-Schloer
    Measurement and Control of Self-organised Behaviour in Robot Swarms. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:209-223 [Conf]
  17. Andrew Sohn, Hukeun Kwak, Kyusik Chung
    Autonomous Learning of Load and Traffic Patterns to Improve Cluster Utilization. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:224-239 [Conf]
  18. Maria Teresa Signes Pont, Juan Manuel García Chamizo, Higinio Mora Mora, Gregorio de Miguel Casado
    Parametric Architecture for Function Calculation Improvement. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:240-253 [Conf]
  19. Guillermo Payá Vayá, Javier Martín-Langerwerf, Piriya Taptimthong, Peter Pirsch
    Design Space Exploration of Media Processors: A Generic VLIW Architecture and a Parameterized Scheduler. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:254-267 [Conf]
  20. Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement
    Modeling of Interconnection Networks in Massively Parallel Processor Architectures. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:268-282 [Conf]
  21. Jan Bosch
    Invited Talk: Expanding Software Product Families: From Integration to Composition. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:283-295 [Conf]
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