Conferences in DBLP
Masayuki Ito , Naofumi Takagi , Shuzo Yajima Efficient Initial Approximation and Fast Converging Methods for Division and Square Root. [Citation Graph (0, 0)][DBLP ] Conf ] Hannes Hassler , Naofumi Takagi Function Evaluation by Table Look-up and Addition. [Citation Graph (0, 0)][DBLP ] Conf ] Debjit Das Sarma , David W. Matula Faithful Bipartite ROM Reciprocal Tables. [Citation Graph (0, 0)][DBLP ] Conf ] H. Bederr , Michael Nicolaidis , Alain Guyot Analytic approach for error masking elimination in on-line multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Michael Owens , Raminder Singh Bajwa , Mary Jane Irwin Reducing the number of counters needed for integer multiplication. [Citation Graph (0, 0)][DBLP ] Conf ] Charles U. Martel , Vojin G. Oklobdzija , R. Ravi , Paul F. Stelling Design Strategies for Optimal Multiplier Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Chung Nan Lyu , David W. Matula Redundant Binary Booth Recoding. [Citation Graph (0, 0)][DBLP ] Conf ] Milos D. Ercegovac , Tomás Lang Sign detection and comparison networks with a small number of transitions. [Citation Graph (0, 0)][DBLP ] Conf ] A. Houelle , Habib Mehrez , N. Vaucher , Luis A. Montalvo , Alain Guyot Application of fast layout synthesis environment to dividers evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Michael J. Flynn , Kevin J. Nowka , G. Bewick , Eric M. Schwarz , Nhon T. Quach The SNAP Project: Towards Sub-Nanosecond Arithmetic. [Citation Graph (0, 0)][DBLP ] Conf ] Belle W. Y. Wei , He Du , Honglu Chen A complex-number multiplier using radix-4 digits. [Citation Graph (0, 0)][DBLP ] Conf ] S. Cui , Neil Burgess , Michael J. Liebelt , Kamran Eshraghian A GaAs IEEE Floating Point Standard Single Precision Multiplier. [Citation Graph (0, 0)][DBLP ] Conf ] Gensoh Matsubara , Nobuhiro Ide , Haruyuki Tago , Seigo Suzuki , Nobuyuki Goto 30-ns 55-b Radix 2 Division and Square Root Using a Self-Timed Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] V. K. Jain , L. Lin High-speed double precision computation of nonlinear functions. [Citation Graph (0, 0)][DBLP ] Conf ] Hercule Kwan , Robert Leonard Nelson Jr. , Earl E. Swartzlander Jr. Cascaded Implementation of an Iterative Inverse--Square--Root Algorithm, with Overflow Lookahead. [Citation Graph (0, 0)][DBLP ] Conf ] Tomás Lang , Paolo Montuschi Very-high radix combined division and square root with prescaling and selection by rounding. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Soderquist , Miriam Leeser An Area/Performance Comparison of Subtractive and Multiplicative Divide/Square Root Implementations. [Citation Graph (0, 0)][DBLP ] Conf ] Tim Coe , Ping Tak Peter Tang It Takes Six Ones To Reach a Flaw. [Citation Graph (0, 0)][DBLP ] Conf ] Robert K. Yu , Gregory B. Zyner 167 MHz Radix-4 Floating Point Multiplier. [Citation Graph (0, 0)][DBLP ] Conf ] J. Arjun Prabhu , Gregory B. Zyner 167 MHz Radix-8 Divide and Square Root Using Overlapped Radix-2 Stages. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Lynch , Ashraf Ahmed , Michael J. Schulte , Thomas K. Callaway , Robert Tisdale The K5 transcendental functions. [Citation Graph (0, 0)][DBLP ] Conf ] Elisardo Antelo , Javier D. Bruguera , Julio Villalba , Emilio L. Zapata Redundant CORDIC Rotator Based on Parallel Prediction. [Citation Graph (0, 0)][DBLP ] Conf ] Feng Zhou , Peter Kornerup High Speed DCT/IDCT Using a Pipelined CORDIC Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Takafumi Hamano , Naofumi Takagi , Shuzo Yajima , Franco P. Preparata O(n)-depth circuit algorithm for modular exponentiation. [Citation Graph (0, 0)][DBLP ] Conf ] Holger Orup Simplifying Quotient Determination in High-Radix Modular Multiplication. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Michel Muller , Arnaud Tisserand , Alexandre Scherbyna Semi-Logarithmic Number Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Rudi van Drunen , Lambert Spaanenburg , Paul G. Lucassen , J. A. G. Nijhuis , Jan Tijmen Udding Arithmetic for Relative Accuracy. [Citation Graph (0, 0)][DBLP ] Conf ] Christoph Baumhof A New VLSI Vector Arithmetic Coprocessor for the PC. [Citation Graph (0, 0)][DBLP ] Conf ] Warren E. Ferguson Exact Computation of a Sum or Difference with Applications to Argument Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Michael J. Schulte , Earl E. Swartzlander Jr. Hardware Design and Arithmetic Algorithms for a Variable-Precision, Interval Arithmetic Coprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Dominique Michelucci An epsilon-Arithmetic for Removing Degeneracies. [Citation Graph (0, 0)][DBLP ] Conf ] 