Conferences in DBLP

IEEE Symposium on Computer Arithmetic (arith)
1999 (conf/arith/1999)

1. Richard P. Brent
   Computer Arithmetic - A Programmer's Perspective. [Citation Graph (0, 0)][DBLP]
   IEEE Symposium on Computer Arithmetic, 1999, pp:2-0 [Conf]
   
2. Shane Story, Ping Tak Peter Tang
   New Algorithms for Improved Transcendental Functions on IA-64. [Citation Graph (0, 0)][DBLP]
   IEEE Symposium on Computer Arithmetic, 1999, pp:4-11 [Conf]
   
3. Martin S. Schmookler, Michael Putrino, Anh Mather, Jon Tyler, Huy Van Nguyen, Charles Roth, Mukesh Sharma, Mydung N. Pham, Jeff Lent
   A Low-Power, High-Speed Implementation of a PowerPC(tm) Microprocessor Vector Extension. [Citation Graph (0, 0)][DBLP]
   IEEE Symposium on Computer Arithmetic, 1999, pp:12-0 [Conf]
   
4. Dhananjay S. Phatak, Israel Koren
   Intermediate Variable Encodings that Enable Multiplexor-Based Implementations of Two Operand Addition. [Citation Graph (0, 0)][DBLP]
   IEEE Symposium on Computer Arithmetic, 1999, pp:22-29 [Conf]
   
5. Simon Knowles
   A Family of Adders. [Citation Graph (0, 0)][DBLP]
   IEEE Symposium on Computer Arithmetic, 1999, pp:30-34 [Conf]
   
6. Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, Cheng-Chew Lim
   Reduced Latency IEEE Floating-Point Standard Adder Architectures. [Citation Graph (0, 0)][DBLP]
   IEEE Symposium on Computer Arithmetic, 1999, pp:35-0 [Conf]
   
7. Alexandre F. Tenca, Milos D. Ercegovac
   On the Design of High-Radix On-Line Division for Long Precision. [Citation Graph (0, 0)][DBLP]
   IEEE Symposium on Computer Arithmetic, 1999, pp:44-51 [Conf]
   
8. Paolo Montuschi, Tomás Lang
   Boosting Very-High Radix Division with Prescaling and Selection by Rounding. [Citation Graph (0, 0)][DBLP]
   IEEE Symposium on Computer Arithmetic, 1999, pp:52-59 [Conf]
   
9. Alberto Nannarelli, Tomás Lang
   Low-Power Division: Comparison among Implementations of Radix 4, 8 and 16. [Citation Graph (0, 0)][DBLP]
   IEEE Symposium on Computer Arithmetic, 1999, pp:60-0 [Conf]
   
10. Thomas Blum
    Montgomery Modular Exponentiation on Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1999, pp:70-77 [Conf]
    
11. Colin D. Walter
    Moduli for Testing Implementations of the RSA Cryptosystem. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1999, pp:78-85 [Conf]
    
12. Naofumi Takagi, Seiji Kuwahara
    Digit-Recurrence Algorithm for Computing Euclidean Norm of a 3-D Vector. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1999, pp:86-0 [Conf]
    
13. Marius A. Cornea-Hasegan, Roger A. Golliver, Peter W. Markstein
    Correctness Proofs Outline for Newton-Raphson Based Floating-Point Divide and Square Root Algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1999, pp:96-105 [Conf]
    
14. Stuart F. Oberman
    Floating Point Division and Square Root Algorithms and Implementation in the AMD-K7 Microprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1999, pp:106-115 [Conf]
    
15. Martin S. Schmookler, Ramesh C. Agarwal, Fred G. Gustavson
    Series Approximation Methods for Divide and Square Root in the Power3(TM) Processor. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1999, pp:116-123 [Conf]
    
16. Michael J. Schulte, Kent E. Wires
    High-Speed Inverse Square Roots. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1999, pp:124-0 [Conf]
    
17. Aryan Saed, Majid Ahmadi, Graham A. Jullien
    Arithmetic with Signed Analog Digits. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1999, pp:134-141 [Conf]
    
18. J. N. Coleman, E. I. Chester
    A 32-Bit Logarithmic Arithmetic Unit and its Performance Compared to Floating-Point. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1999, pp:142-151 [Conf]
    
19. Peter Kornerup
    Necessary and Sufficient Conditions for Parallel, Constant Time Conversion and Addition. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1999, pp:152-0 [Conf]
    
20. Reto Zimmermann
    Efficient VLSI Implementation of Modulo (2^n=B11) Addition and Multiplication. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1999, pp:158-167 [Conf]
    
21. M. Bhardwaj, T. Srikanthan, C. T. Clarke
    A Reverse Converter for the 4-moduli Superset {2^n-1, 2^n, 2^n+1, 2^(n+1)+1}. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1999, pp:168-175 [Conf]
    
22. M. Bhardwaj, T. Srikanthan, C. T. Clarke
    VLSI Costs of Arithmetic Parallelism: A Residue Reverse Conversion Perspectiv. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1999, pp:176-0 [Conf]
    
23. Javier Hormigo, Julio Villalba, Emilio L. Zapata
    Interval Sine and Cosine Functions Computation Based on Variable-Precision CORDIC Algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1999, pp:186-193 [Conf]
    
24. David Lewis
    Complex Logarithmic Number System Arithmetic Using High-Radix Redundant CORDIC Algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1999, pp:194-203 [Conf]
    
25. Elisardo Antelo, Tomás Lang, Javier D. Bruguera
    Very-High Radix CORDIC Vectoring with Scalings and Selection by Rounding. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1999, pp:204-0 [Conf]
    
26. Jeng-Jong J. Lue, Dhananjay S. Phatak
    Area x Delay (A T) Efficient Multiplier Based on an Intermediate Hybrid Signed-Digit (HSD-1) Representation. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1999, pp:216-224 [Conf]
    
27. Guy Even, Peter-Michael Seidel
    A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1999, pp:225-232 [Conf]
    
28. Cristina Iordache, David W. Matula
    On Infinitely Precise Rounding for Division, Square Root, Reciprocal and Square Root Reciprocal. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1999, pp:233-240 [Conf]
    
29. Michael Parks
    Number-Theoretic Test Generation for Directed Rounding. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1999, pp:241-0 [Conf]
    
30. Marc Daumas
    Multiplications of Floating Point Expansions. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1999, pp:250-257 [Conf]
    
31. Eric M. Schwarz, Ronald M. Smith, Christopher A. Krygowski
    The S/390 G5 Floating Point Unit Supporting Hex and Binary Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1999, pp:258-265 [Conf]
    
32. Guenter Gerwig, Michael Kroener
    Floating-Point Unit in Standard Cell Design with 116 Bit Wide Dataflow. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 1999, pp:266-0 [Conf]