Conferences in DBLP
Peter M. Kogge , Toshio Sunaga , Hisatada Miyataka , Koji Kitamura , Eric Retter Combined DRAM and logic chip for massively parallel systems. [Citation Graph (0, 0)][DBLP ] Conf ] Huy Cat , Myunghee Lee , Brent Buchanan , D. Scott Wills , Martin A. Brooke , Nan M. Jokerst Silicon VLSI processing architectures incorporating integrated optoelectronic devices. [Citation Graph (0, 0)][DBLP ] Conf ] M. Bolotski , T. Simon , C. Vieri , R. Amirtharajah , Thomas F. Knight Jr. Abacus: a 1024 processor 8 ns SIMD array. [Citation Graph (0, 0)][DBLP ] Conf ] Chris J. Myers , Tomas Rokicki , Teresa H. Y. Meng Automatic synthesis of gate-level timed circuits with choice. [Citation Graph (0, 0)][DBLP ] Conf ] Robert M. Fuhrer , Bill Lin , Steven M. Nowick Algorithms for the optimal state assignment of asynchronous state machines. [Citation Graph (0, 0)][DBLP ] Conf ] Erik Brunvand Low latency self-timed flow-through FIFOs. [Citation Graph (0, 0)][DBLP ] Conf ] Jae-Tack Yoo , Ganesh Gopalakrishnan , Kent F. Smith , V. John Mathews High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chips. [Citation Graph (0, 0)][DBLP ] Conf ] Gert Cauwenberghs Bit-serial bidirectional A/D/A conversio. [Citation Graph (0, 0)][DBLP ] Conf ] Hans Lindkvist , Per Andersson Dynamic CMOS circuit techniques for delay and power reduction in parallel adders . [Citation Graph (0, 0)][DBLP ] Conf ] Gary C. Moyer , Mark Clements , Wentai Liu , Toby Schaffer , Ralph K. Cavin III A technique for high-speed, fine-resolution pattern generation and its CMOS implementation. [Citation Graph (0, 0)][DBLP ] Conf ] H. Dhanesha , K. Falakshahi , Mark Horowitz Array-of-arrays architecture for parallel floating point multiplication. [Citation Graph (0, 0)][DBLP ] Conf ] John Lazzaro , John Wawrzynek A multi-sender asynchronous extension to the AER protocol. [Citation Graph (0, 0)][DBLP ] Conf ] Louis Monier , Ramsey W. Haddad , Jeremy Dion Recursive layout generation. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjay Rekhi , J. Donald Trotter HAL: heuristic algorithms for layout synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] X. Cai , Keith Nabors , Jacob White Efficient Galerkin techniques for multipole-accelerated capacitance extraction of 3-D structures with multiple dielectrics. [Citation Graph (0, 0)][DBLP ] Conf ] Alex G. Dickinson , Bryan D. Ackland , El-Sayed Eid , David A. Inglis , Eric R. Fossum Standard CMOS active pixel image sensors for multimedia applications. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas G. Andreou , Kwabena Boahen A 590, 000 transistor 48, 000 pixel, contrast sensitive, edge enhancing, CMOS imager-silicon retina. [Citation Graph (0, 0)][DBLP ] Conf ] Tonia G. Morris , Denise M. Wilson , Stephen P. DeWeerth Analog VLSI circuits for manufacturing inspection. [Citation Graph (0, 0)][DBLP ] Conf ] Huy Nguyen , Abhijit Chatterjee OPTIMUS: a new program for OPTIMizing linear circuits with number-splitting and shift-and-add decompositions. [Citation Graph (0, 0)][DBLP ] Conf ] Stan Y. Liao , Srinivas Devadas , Kurt Keutzer Code density optimization for embedded DSP processors using data compression techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Timothy J. Stanley , Trevor N. Mudge Systematic objective-driven computer architecture optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Larry R. Dennison , William J. Dally , Thucydides Xanthopoulos Low-latency plesiochronous data retiming. [Citation Graph (0, 0)][DBLP ] Conf ] Gill A. Pratt , John Nguyen Distributed synchronous clocking. [Citation Graph (0, 0)][DBLP ] Conf ] Kei-Yong Khoo , Alan N. Willson Jr. Single-transistor transparent-latch clocking. [Citation Graph (0, 0)][DBLP ] Conf ] Carl Ebeling , Brian Lockyear On the performance of level-clocked circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ted Stanion , Carl Sechen Quasi-algebraic decompositions of switching functions. [Citation Graph (0, 0)][DBLP ] Conf ] Kumar N. Lalgudi , Marios C. Papaefthymiou Efficient retiming under a general delay model. [Citation Graph (0, 0)][DBLP ] Conf ] Scott Hauck , Gaetano Borriello An evaluation of bipartitioning techniques. [Citation Graph (0, 0)][DBLP ] Conf ] S. G. Younis , Thomas F. Knight Jr. Non-dissipative rail drivers for adiabatic circuits. [Citation Graph (0, 0)][DBLP ] Conf ] William C. Athas , Nestoras Tzartzanis Energy recovery for low-power CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] José Monteiro , John Rinderknecht , Srinivas Devadas , Abhijit Ghosh Optimization of combinational and sequential logic circuits for low power using precomputation. [Citation Graph (0, 0)][DBLP ] Conf ] 