Conferences in DBLP

Advanced Research in VLSI (arvlsi)
1997 (conf/arvlsi/1997)

1. Daniel W. Dobberpuhl
   Circuits and Technology for Digital's StrongARM(tm) and ALPHA Microprocessors. [Citation Graph (0, 0)][DBLP]
   ARVLSI, 1997, pp:2-11 [Conf]
   
2. David Parry
   Scalability in computing for today and tomorrow. [Citation Graph (0, 0)][DBLP]
   ARVLSI, 1997, pp:12-31 [Conf]
   
3. V. Chandramouli, Karem A. Sakallah, Ayman I. Kayssi
   Signal Delay in Coupled, Distributed RC Lines in the Presence of Temporal Proximity. [Citation Graph (0, 0)][DBLP]
   ARVLSI, 1997, pp:32-46 [Conf]
   
4. Allen E. Sjogren, Chris J. Myers
   Interfacing Synchronous and Asynchronous Modules Within a High-Speed Pipeline. [Citation Graph (0, 0)][DBLP]
   ARVLSI, 1997, pp:47-61 [Conf]
   
5. Les Hall, Mark Clements, Wentai Liu, Griff L. Bilbro
   Clock Distribution Using Cooperative Ring Oscillators. [Citation Graph (0, 0)][DBLP]
   ARVLSI, 1997, pp:62-77 [Conf]
   
6. B. Chester Hwang
   Trends of Key Advanced Device Technologies. [Citation Graph (0, 0)][DBLP]
   ARVLSI, 1997, pp:78-81 [Conf]
   
7. Chandra Tan, Donald W. Bouldin, Peyman H. Dehkordi
   Design Implementation of Intrinsic Area Array ICs. [Citation Graph (0, 0)][DBLP]
   ARVLSI, 1997, pp:82-95 [Conf]
   
8. Alejandro F. González, Pinaki Mazumder
   Compact Signed-Digit Adder Using Multiple-Valued Logic. [Citation Graph (0, 0)][DBLP]
   ARVLSI, 1997, pp:96-113 [Conf]
   
9. Todd Hinck, Allyn E. Hubbard
   Image Edge Enhancement, Dynamic Compression and Noise Suppression using Analog Circuit Processing. [Citation Graph (0, 0)][DBLP]
   ARVLSI, 1997, pp:114-126 [Conf]
   
10. George Kornaros, Christoforos E. Kozyrakis, Panagiota Vatsolaki, Manolis Katevenis
    Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1997, pp:127-144 [Conf]
    
11. David M. Dahle, Jeffrey D. Hirschberg, Kevin Karplus, Hansjörg Keller, Eric Rice, Don Speck, Douglas H. Williams, Richard Hughey
    Kestrel: Design of an 8-bit SIMD Parallel Processor. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1997, pp:145-0 [Conf]
    
12. Alain J. Martin, Andrew Lines, Rajit Manohar, Mika Nyström, Paul I. Pénzes, Robert Southworth, Uri Cummings
    The Design of an Asynchronous MIPS R3000 Microprocessor. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1997, pp:164-181 [Conf]
    
13. Stephen P. DeWeerth, Girish N. Patel, Mario F. Simoni, David E. Schimmel, Ronald L. Calabrese
    A VLSI Architecture for Modeling Intersegmental Coordination. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1997, pp:182-200 [Conf]
    
14. Hans M. Jacobson, Ganesh Gopalakrishnan
    Asynchronous Microengines for Efficient High-level Control. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1997, pp:201-218 [Conf]
    
15. Martin Benes, Andrew Wolfe, Steven M. Nowick
    A High-Speed Asynchronous Decompression Circuit for Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1997, pp:219-237 [Conf]
    
16. Nathan Shnidman, William H. Mangione-Smith, Miodrag Potkonjak
    Fault Scanner for Reconfigurable Logic. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1997, pp:238-255 [Conf]
    
17. Waleed Meleis, Miriam Leeser, Paul M. Zavracky, Mankuan Michael Vai
    Architectural Design of a Three Dimensional FPGA. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1997, pp:256-269 [Conf]
    
18. Behzad Razavi
    Next-Generation RF Circuits and Systems. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1997, pp:270-283 [Conf]
    
19. Kevin J. Nowka, H. Peter Hofstee
    Circuits and Microarchitecture for Gigahertz VLSI Designs. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1997, pp:284-287 [Conf]
    
20. John Poulton
    An Embedded DRAM for CMOS ASICs. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1997, pp:288-302 [Conf]
    
21. Tadaaki Yamauchi, Lance Hammond, Kunle Olukotun
    The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1997, pp:303-319 [Conf]