Conferences in DBLP

Advanced Research in VLSI (arvlsi)
2001 (conf/arvlsi/2001)

1. Euiseok Kim, Jeong-Gun Lee, Dong-Ik Lee
   Building a Distributed Asynchronous Control Unit through Automatic Derivation of Hierarchically Decomposed AFSMs from a CDFG. [Citation Graph (0, 0)][DBLP]
   ARVLSI, 2001, pp:2-15 [Conf]
   
2. Rajit Manohar, Mika Nyström, Alain J. Martin
   Precise Exceptions in Asynchronous Processors. [Citation Graph (0, 0)][DBLP]
   ARVLSI, 2001, pp:16-28 [Conf]
   
3. V. A. Bartlett, Eckhard Grass
   A Low-Power Asynchronous VLSI FIR Filter. [Citation Graph (0, 0)][DBLP]
   ARVLSI, 2001, pp:29-41 [Conf]
   
4. Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou
   Design, Verification, and Test of a True Single-Phase 8-bit Adiabatic Multiplier. [Citation Graph (0, 0)][DBLP]
   ARVLSI, 2001, pp:42-58 [Conf]
   
5. Seongmoo Heo, Ronny Krashinsky, Krste Asanovic
   Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy. [Citation Graph (0, 0)][DBLP]
   ARVLSI, 2001, pp:59-74 [Conf]
   
6. K. Joseph Hass, Jack Venbrux, Prakash Bhatia
   Logic Design Considerations for 0.5-Volt CMOS. [Citation Graph (0, 0)][DBLP]
   ARVLSI, 2001, pp:75-87 [Conf]
   
7. Thaddeus Gabara
   Phantom Mode Signaling in VLSI Systems. [Citation Graph (0, 0)][DBLP]
   ARVLSI, 2001, pp:88-100 [Conf]
   
8. Claude R. Gauthier, Jayakumaran Sivagnaname, Richard B. Brown
   Dynamic Receiver Biasing For Inter-Chip Communication. [Citation Graph (0, 0)][DBLP]
   ARVLSI, 2001, pp:101-111 [Conf]
   
9. Rajit Manohar
   Width-Adaptive Data Word Architectures. [Citation Graph (0, 0)][DBLP]
   ARVLSI, 2001, pp:112-131 [Conf]
   
10. Chris Winstead, Jie Dai, Woo Jin Kim, Scott Little, Yong-Bin Kim, Chris J. Myers, Christian Schlegel
    Analog MAP Decoder for (8, 4) Hamming Code in Subthreshold CMOS. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 2001, pp:132-147 [Conf]
    
11. Matt Kucic, Paul E. Hasler, Jeff Dugger, David V. Anderson
    Programmable and Adaptive Analog Filters using Arrays of Floating-Gate Circuits. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 2001, pp:148-162 [Conf]
    
12. Vincent F. Koosh, Rodney M. Goodman
    Dynamic Charge Restoration of Floating Gate Subthreshold MOS Translinear Circuits. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 2001, pp:163-171 [Conf]
    
13. Sree Ganesan, Ranga Vemuri
    Analog-Digital Partitioning for Field-Programmable Mixed Signal Systems. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 2001, pp:172-187 [Conf]
    
14. Kip C. Killpack, Eric Mercer, Chris J. Myers
    A Standard-Cell Self-Timed Multiplier for Energy and Area Critical Synchronous Systems. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 2001, pp:188-201 [Conf]
    
15. Chan-Ho Park, Byung-Soo Choi, Dong-Ik Lee, Ho-Yong Choi
    Asynchronous Array Multiplier with an Asymmetric Parallel Array Structure. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 2001, pp:202-212 [Conf]
    
16. Sheng Sun, Larry McMurchie, Carl Sechen
    A High-Performance 64-bit Adder Implemented in Output Prediction Logic. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 2001, pp:213-223 [Conf]
    
17. Marc Cohen, Gert Cauwenberghs, Mikhail Vorontsov, Gary Carhart
    Focal-Plane Image and Beam Quality Sensors for Adaptive Optics. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 2001, pp:224-237 [Conf]
    
18. Alberto Pesavento, Christof Koch
    Methods and Circuits for Focal-Plane Computation of Features in CMOS Visual Sensors. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 2001, pp:238-248 [Conf]
    
19. Oliver Landolt, Ania Mitros, Christof Koch
    Visual Sensor with Resolution Enhancement by Mechanical Vibrations. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 2001, pp:249-264 [Conf]