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Conferences in DBLP
- Ruby B. Lee
Challenges in the Design of Security-Aware Processors. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:2-0 [Conf]
- Hylke W. van Dijk, Henk J. Sips, Ed F. Deprettere
Context-Aware Process Networks. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:6-16 [Conf]
- Sven Verdoolaege, Maurice Bruynooghe, Gerda Janssens, Francky Catthoor
Multi-dimentsional Incremetal Loops Fusion for Data Locality. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:17-27 [Conf]
- Lakshminarayanan Renganarayanan, Sanjay V. Rajopadhye
Switched Memory Architectures-Moving Beyond Systolic Arrays. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:28-39 [Conf]
- Anne-Claire Guillou, Patrice Quinton, Tanguy Risset
Hardware Synthesis for Multi-Dimensional Time. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:40-50 [Conf]
- Thorsten Dräger, Gerhard Fettweis
Using Group Theory to Specify Application Specific Interconnection Networks for SIMD DSPs. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:51-0 [Conf]
- Kevin Fan, Nathan Clark, Michael L. Chu, K. V. Manjunath, Rajiv A. Ravindran, Mikhail Smelyanskiy, Scott A. Mahlke
Systematic Register Bypass Customization for Application-Specific Processors. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:64-74 [Conf]
- Alexandru Turjan, Bart Kienhuis
Storage Management in Process Networks using the Lexicographically Maximal Preimage. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:75-85 [Conf]
- José L. Ayala, Marisa Luisa López-Vallejo, Alexander V. Veidenbaum, Carlos A. Lopez
Energy Aware Register File Implementation through Instruction Predecode. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:86-96 [Conf]
- Terry Tao Ye, Giovanni De Micheli
Physical Planning for On-Chip Multiprocessor Networks and Switch Fabrics. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:97-107 [Conf]
- Armita Peymandoust, Laura Pozzi, Paolo Ienne, Giovanni De Micheli
Automatic Instruction Set Extension and Utilization for Embedded Processors. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:108-0 [Conf]
- Toshishige Yamada, M. Meyyappan
Nanotechnology in the Development of Future Computing Systems. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:120-124 [Conf]
- David B. Janes, Subhasis Ghosh, Jaewon Choi, Saurabh Lodha
Circuit Characteristics of Molecular Electronic Components. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:125-131 [Conf]
- Seth Copen Goldstein, Mihai Budiu, Mahim Mishra, Girish Venkataramani
Reconfigurable Computing and Electronic Nanotechnology. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:132-0 [Conf]
- James Irwin, Dan Page
Using Media Processors for Low-Memory AES Implementation. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:144-154 [Conf]
- Piia Simonen, Ilkka Saastamoinen, Jari Nurmi
Variable-Length Instruction Compression for Area Minimization. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:155-160 [Conf]
- Andreas Wieferink, Tim Kogel, Achim Nohl, Andreas Hoffmann
Generic Tool-Set for SoC Mulitiprocessor Debugging and Synchronization. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:161-171 [Conf]
- Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt
Evaluating Memory Architectures for Media Applications on Coarse-Grained Recon.gurable Architectures. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:172-182 [Conf]
- Rama Sangireddy, Arun K. Somani
Application-Specific Computing with Adaptive Register File Architectures. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:183-0 [Conf]
- Zhaohui Liu, Kevin Dickson, John V. McCanny
A floating-point CORDIC based SVD processor. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:194-203 [Conf]
- Michael J. Schulte, Louis Marquette, Shankar Krithivasan, E. George Walters III, John Glossner
Combined Multiplication and Sum-of-Squares Units. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:204-214 [Conf]
- Abhishek Singh, Dhananjay S. Phatak, Tom Goff, Mike Riggs, James F. Plusquellic, Chintan Patel
Comparison of Branching CORDIC Implementations. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:215-225 [Conf]
- Lai-Sze Au, Neil Burgess
Unified Radix-4 Multiplier for GF(p) and GF(2^n). [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:226-236 [Conf]
- Zhijie Shi, Xiao Yang, Ruby B. Lee
Arbitrary Bit Permutations in One or Two Cycles. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:237-0 [Conf]
- Mihai Sima, Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven
Color Space Conversion for MPEG decoding on FPGA-augmented TriMedia Processor. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:250-259 [Conf]
- Vikram Chandrasekhar, Frank Livingston, Joseph R. Cavallaro
Reducing dynamic power consumption in next generation DS-CDMA mobile communication receivers. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:260-270 [Conf]
- P. H. Chan Patton, Jack Y. B. Lee
An Efficient Disk-Array-Based Server Design for a Multicast Video Streaming System. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:271-281 [Conf]
- Jung-Yup Kang, Sandeep Gupta, Saurabh Shah, Jean-Luc Gaudiot
An Efficient PIM (Processor-In-Memory) Architecture for Motion Estimation. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:282-292 [Conf]
- Swee Yeow, John V. McCanny
A VLSI Architecture for Advanced Video Coding Motion Estimation. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:293-0 [Conf]
- Jean-Michel Muller
Complex Division with Prescaling of Operands. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:304-314 [Conf]
- Mark G. Arnold
Iterative Methods for Logarithmic Subtraction. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:315-525 [Conf]
- Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
A Family of Parallel-Pre.x Modulo 2n - 1 Adders. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:326-336 [Conf]
- Chichyang Chen, Rui-Lin Chen
Performance-Improved Computation of Very Large Word-Length LNS Addition/Subtraction Using Signed-Digit Arithmetic. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:337-347 [Conf]
- Mark A. Erle, Michael J. Schulte
Decimal Multiplication Via Carry-Save Addition. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:348-0 [Conf]
- Yiqun Zhu, Mohammed Benaissa
Reconfigurable Viterbi Decoding Using a New ACS Pipelining Technique. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:360-368 [Conf]
- Kyung Lan Heo, Sung M. Cho, Jung Hoo Lee, Myung Hoon Sunwoo
Application-Specific DSP Architecture For Fast Fourier Transform. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:369-377 [Conf]
- Ayman M. El-Khashab, Earl E. Swartzlander Jr.
An Architecture for a Radix-4 Modular Pipeline Fast Fourier Transform. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:378-388 [Conf]
- George Kornaros, Theofanis Orphanoudakis, Ioannis Papaefstathiou
GFS: An Efficient Implementation of Fair Scheduling for Mult-Gigabit Packet Networks. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:389-399 [Conf]
- Viktor Bunimov, Manfred Schimmler
Area and Time Efficient Modular Multiplication of Large Integers. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:400-0 [Conf]
- Jean-luc Beauchat
Modular Multiplication for FPGA Implementation of the IDEA Block Cipher. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:412-422 [Conf]
- Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri
Concurrent Fault Detection in a Hardware Implementation of the RC5 Encryption Algorithm. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:423-432 [Conf]
- Siddika Berna Örs, Lejla Batina, Bart Preneel, Joos Vandewalle
Hardware Implementation of an Elliptic Curve Processor over GF(p). [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:433-443 [Conf]
- Hans Eberle, Nils Gura, Sheueling Chang Shantz
A Cryptograhpic Processor for Arbitrary Elliptic Curves over. [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:444-454 [Conf]
- Johann Großschädl, Guy-Armand Kamendje
Instruction Set Extension for Fast Elliptic Curve Cryptography over Binary Finite Fields GF(2m). [Citation Graph (0, 0)][DBLP]
ASAP, 2003, pp:455-0 [Conf]
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