Conferences in DBLP
Kevin P. Acken , Heung-Nam Kim , Mary Jane Irwin , Robert Michael Owens An Architectural Design For Parallel Fractal Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Valerie E. Taylor , Jian Chen , Thomas Canfield , Rick L. Stevens A Decomposition Method For Efficient Use Of Distributed Supercomputers For Finite Element Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey D. Hirschberg , Richard Hughey , Kevin Karplus , Don Speck Kestrel: A Programmable Array for Sequence Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Hyesook Lim , Changhoon Yim , Earl E. Swartzlander Jr. Finite Word-Length Effects Of An Unified Systolic Array For 2-D DCT/IDCT. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Claude Bajard , Laurent-Stéphane Didier , Jean-Michel Muller A New Euclidean Division Algorithm For Residue Number Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Julio Villalba , J. C. Arrabal , Emilio L. Zapata , Elisardo Antelo , Javier D. Bruguera Radix-4 Vectoring Cordic Algorithm And Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Kevin P. Acken , Mary Jane Irwin , Robert Michael Owens , Amulya K. Garga Architectural Optimizations For A Floating Point Multiply-Accumulate Unit In A Graphics Pipeline. [Citation Graph (0, 0)][DBLP ] Conf ] Leilei Song , Keshab K. Parhi Efficient Finite Field Serial/Parallel Multiplication. [Citation Graph (0, 0)][DBLP ] Conf ] Colin C. W. Hui , Tiong Jiu Ding , John V. McCanny , Roger F. Woods A New FFT Architecture and Chip Design for Motion Compensation based on Phase Correlation. [Citation Graph (0, 0)][DBLP ] Conf ] David A. Parker , Keshab K. Parhi Area-Efficient Parallel FIR Digital Filter Implementations. [Citation Graph (0, 0)][DBLP ] Conf ] Jan Peter Berns , Tobias G. Noll A Flexible Motion Estimation Chip for Variable Size Block Matching. [Citation Graph (0, 0)][DBLP ] Conf ] Hangu Yeo , Yu Hen Hu A Novel Matching Criterion And Low Power Architecture For Real-Time Block Based Motion Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Jürgen Teich , Lothar Thiele , Li Zhang Scheduling of Partitioned Regular Algorithms on Processor Arrays with Constrained Resources. [Citation Graph (0, 0)][DBLP ] Conf ] Pascal Faudemay , Laurent Winckel An Abstract Model for a Low Cost SIMD Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Hyuk-Jae Lee , José A. B. Fortes Automatic Generation of Modular Mappings. [Citation Graph (0, 0)][DBLP ] Conf ] Montserrat Bóo , Francisco Argüello , Javier D. Bruguera , Emilio L. Zapata High-Speed Viterbi Decoder: An Efficient Scheduling Method to Exploit the Pipelining. [Citation Graph (0, 0)][DBLP ] Conf ] Nicolas Hubart Monitoring and Debugging a Hard Real-Time Distributed Computer for Aircraft Industry. [Citation Graph (0, 0)][DBLP ] Conf ] Shietung Peng , Stanislav Sedukhin , Igor S. Sedukhin Parallel Algorithm And Architecture For Two-Step Division-Free Gaussian Elimination. [Citation Graph (0, 0)][DBLP ] Conf ] Mohan Vishwanath , Robert Michael Owens A Common Architecture For The DWT and IDWT. [Citation Graph (0, 0)][DBLP ] Conf ] Guy Even , Ami Litman Overcoming chip-to-chip delays and clock skews. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Trane Diagnosis Algorithm for Mobility-Oriented System. [Citation Graph (0, 0)][DBLP ] Conf ] Minesh I. Patel , N. Ranganathan A VLSI System Architecture For Real-Time Intelligent Decision Making. [Citation Graph (0, 0)][DBLP ] Conf ] A. Wang , K. Yao , R. E. Hudson , D. Korompis , F. Lorenzelli , S. Soli , S. Gao Microphone Array for Hearing Aid and Speech Enhancement Applications. [Citation Graph (0, 0)][DBLP ] Conf ] David R. Surma , Edwin Hsing-Mean Sha Static Communication Scheduling for Minimizing Collisions in Application Specific Parallel Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Daping Song , Thierry Divoux , Francis LePage Design of the Distributed Architecture of a Machine-tool Using FIP Fieldbus. [Citation Graph (0, 0)][DBLP ] Conf ] Karl M. Fant , Scott A. Brandt NULL Convention Logic/sup TM/: A Complete And Consistent Logic For Asynchronous Digital Circuit Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Reiner W. Hartenstein , Jürgen Becker , Michael Herz , Rainer Kress , Ulrich Nageldinger A Synthesis System For Bus-Based Wavefront Array Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] David R. Smith Hardware Synthesis From Encapsulated Verilog Modules. [Citation Graph (0, 0)][DBLP ] Conf ] Bradly K. Fawcett , J. Watson Reconfigurable Processing With Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Naren Narasimhan , Vinoo Srinivasan , Madhavi Vootukuru , Jeffrey Walrath , Sriram Govindarajan , Ranga Vemuri Rapid Prototyping of Reconfigurable Coprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey Walrath Performance Modeling and Tradeoff Analysis During Rapid Prototyping. [Citation Graph (0, 0)][DBLP ] Conf ] Hylke W. van Dijk , Gerben J. Hekstra , Ed F. Deprettere Jacobi-Specific Processor Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] James E. Beck , Daniel P. Siewiorek A Coalescing-Partitioning Algorithm for Optimizing Processor Specification and Task Allocation. [Citation Graph (0, 0)][DBLP ] Conf ] Pierre-Yves Calland , Alain Darte , Yves Robert , Frédéric Vivien On the Removal of Anti and Output Dependences. [Citation Graph (0, 0)][DBLP ] Conf ] Shuvra S. Bhattacharyya , Sundararajan Sriram , Edward A. Lee Latency-constrained Resynchronization for Multiprocessor DSP Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Florent de Dinechin , Sophie Robert Hierarchical Static Analysis Of Structured Systems Of Affine Recurrence Equations. [Citation Graph (0, 0)][DBLP ] Conf ] Patrice Quinton , Sanjay V. Rajopadhye , Tanguy Risset Extension Of The Alpha Language To Recurrences On Sparse Periodic Domains. [Citation Graph (0, 0)][DBLP ] Conf ] Edin Hodzic , Weijia Shang On Supernode Transformation with Minimized Total Running Time. [Citation Graph (0, 0)][DBLP ] Conf ] Philippe Clauss , Vincent Loechner Parametric Analysis of Polyhedral Iteration Spaces. [Citation Graph (0, 0)][DBLP ] Conf ] 