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Conferences in DBLP

Application-Specific Systems, Architectures, and Processors (asap)
1997 (conf/asap/1997)

  1. Michael Zeller, James C. Phillips, A. Dalke, W. Humphrey, Klaus Schulten, Thomas S. Huang, Vladimir Pavlovic, Yunxin Zhao, Zion Lo, Stephen M. Chu, Rajeev Sharma
    A Visual Computing Environment for Very Large Scale Biomolecular Modeling. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:3-0 [Conf]
  2. Vwani P. Roychowdhury, M. P. Anantram
    On Computing With Locally-Interconnected Architectures in Atomic/Nanoelectronic Systems. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:14-23 [Conf]
  3. Hercule Kwan, Edward J. Powers, Earl E. Swartzlander Jr.
    Realization of a nonlinear digital filter on a DSP array processor. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:24-33 [Conf]
  4. Hyunman Chang, Soohwan Ong, Myung Hoon Sunwoo
    A Linear Array Parallel Image Processor: SliM-II. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:34-41 [Conf]
  5. D. Noguet
    A massively parallel implementation of the watershed based on cellular automata. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:42-52 [Conf]
  6. Edwin Rijpkema, Gerben J. Hekstra, Ed F. Deprettere, Jun Ma
    A strategy for determining a Jacobi specific dataflow processor. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:53-0 [Conf]
  7. Eddy de Greef, Francky Catthoor, Hugo De Man
    Array Placement for Storage Size Reduction in Embedded Multimedia Systems. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:66-75 [Conf]
  8. Yuan-Hau Yeh, Chen-Yi Lee
    Buffer size optimization for full-search block matching algorithms. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:76-85 [Conf]
  9. Carolina Miro, Nicolas Darbel, Renaud Pacalet, Valerie Paquet
    A VLSI Architecture for Image Geometrical Transformations Using an Embedded Core Based Processor. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:86-95 [Conf]
  10. Yeong-Kang Lai, Liang-Gee Chen, Yung-Pin Lee
    A flexible data-interlacing architecture for full-search block-matching algorithm. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:96-0 [Conf]
  11. Roberto R. Osorio, Javier D. Bruguera
    New arithmetic coder/decoder architectures based on pipelining. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:106-115 [Conf]
  12. Ansgar Drolshagen, H. Henkelmann, Walter Anheier
    Processor Elements for the Standard Cell Implementation of Residue Number Systems. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:116-123 [Conf]
  13. Julio Villalba, Tomás Lang
    Low latency word serial CORDIC. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:124-131 [Conf]
  14. Tomás Lang, Elisardo Antelo
    CORDIC-based computation of arccos and arcsin. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:132-143 [Conf]
  15. Michael J. Schulte, James E. Stine
    Accurate Function Approximations by Symmetric Table Lookup and Addition. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:144-153 [Conf]
  16. Christian V. Schimpfle, Sven Simon, Josef A. Nossek
    Low Power CORDIC Implementation Using Redundant Number Representation. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:154-161 [Conf]
  17. B. Haller, J. Goetze, Joseph R. Cavallaro
    Efficient Implementation of Rotation Operations for High Performance QRD-RLS Filtering. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:162-0 [Conf]
  18. Luc Bougé, David Cachera
    A logical framework to prove properties of Alpha programs. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:187-198 [Conf]
  19. Dirk Fimmel, Renate Merker
    Determination of the Processor Functionality in the Design of Processor Arrays. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:199-208 [Conf]
  20. Rumen Andonov, Nicola Yanev, Hafid Bourzoufi
    Three-dimensional orthogonal tile sizing problem: mathematical programming approach. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:209-218 [Conf]
  21. Uwe Eckhardt, Renate Merker
    Scheduling in Co-Partitioned Array Architectures. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:219-228 [Conf]
  22. Pierre-Yves Calland, Jack Dongarra, Yves Robert
    Tiling with limited resources. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:229-238 [Conf]
  23. Florent de Dinechin
    Libraries of schedule-free operators in Alpha. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:239-0 [Conf]
  24. Shuvra S. Bhattacharyya, Praveen K. Murthy, Edward A. Lee
    Optimized software synthesis for synchronous dataflow. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:250-262 [Conf]
  25. Richard S. Stevens
    The Processing Graph Method Tool (PGMT). [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:263-271 [Conf]
  26. Helvio P. Peixoto, Margarida F. Jacome
    Algorithm and architecture-level design space exploration using hierarchical data flows. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:272-282 [Conf]
  27. Jens Horstmannshoff, Thorsten Grötker, Heinrich Meyr
    Mapping multirate dataflow to complex RT level hardware models. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:283-0 [Conf]
  28. Carsten Reuter, M. Schwiegershausen, Peter Pirsch
    Heterogeneous Multiprocessor Scheduling and Allocation using Evolutionary Algorithms. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:294-303 [Conf]
  29. Dolors Royo, Miguel Valero-García, Antonio González, Carme Mari
    A Methodology for User-Oriented Scalability Analysis. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:304-315 [Conf]
  30. Terry Disz, Robert Olson, Rick L. Stevens
    Performance model of the Argonne Voyager multimedia server. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:316-327 [Conf]
  31. Jian Chen, Valerie E. Taylor
    PART: a partitioning tool for efficient use of distributed systems. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:328-337 [Conf]
  32. Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf
    An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:338-349 [Conf]
  33. Corinne Ancourt, Denis Barthou, Christophe Guettier, François Irigoin, Bertrand Jeannet, Jean Jourdan, Juliette Mattioli
    Automatic data mapping of signal processing applications. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:350-0 [Conf]
  34. Carl Ebeling, Darren C. Cronquist, Paul Franklin
    Configurable computing: the catalyst for high-performance architectures. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:364-373 [Conf]
  35. Luca Breveglieri, Luigi Dadda, Vincenzo Piuri
    Fast Arithmetic and Fault Tolerance in the FERMI System. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:374-383 [Conf]
  36. M. Cavadini, M. Wosnitza, Markus Thaler, Gerhard Tröster
    A Multiprocessor System for Real Time High Resolution Image Correlation. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:384-391 [Conf]
  37. Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger
    A Novel Sequencer Hardware for Application Specific Computing. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:392-401 [Conf]
  38. Cristiano C. de Araujo, Marcus V. D. dos Santos, Edna Barros
    A FPGA-based Implementation of an Intravenous Infusion Controller System. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:402-411 [Conf]
  39. Stephanie Dogimont, M. Gumm, Friederich Mombers, Daniel Mlynek, A. Torielli
    Conception and design of a RISC CPU for the use as embedded controller within a parallel multimedia architecture. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:412-421 [Conf]
  40. Andy Negoi, Alain Guyot, Jacques Zimmermann
    A dedicated circuit for charged particles simulation using the Monte Carlo method. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:422-431 [Conf]
  41. Mike Parks
    A Modular Element for Shared Buffer ATM Switch Fabrics. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:432-0 [Conf]
  42. Michael Gansen, Frank Richter, Oliver Weiss, Tobias G. Noll
    A Datapath Generator for Full-Custom Macros of Iterative Logic Arrays. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:438-447 [Conf]
  43. Stefan Pees, Martin Vaupel, Vojin Zivojnovic, Heinrich Meyr
    On core and more: a design perspective for systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:448-457 [Conf]
  44. Herbert Dawid, Klaus-Jürgen Koch, Johannes Stahl
    ADPCM codec: from system level description to versatile HDL model. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:458-467 [Conf]
  45. Gerhard Fettweis
    Design methodology for digital signal processing. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:468-0 [Conf]
  46. Peter M. Kuhn, Andreas Weisgerber, Robert Poppenwimmer, Walter Stechele
    A flexible VLSI architecture for variable block size segment matching with luminance correction. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:479-488 [Conf]
  47. Peter Rieder, Josef A. Nossek
    Implementation of Orthogonal Wavelet Transforms and their Applications. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:489-498 [Conf]
  48. Manuel Sánchez, Juan López, Oscar G. Plata, Emilio L. Zapata
    An efficient architecture for the in place fast cosine transform. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:499-508 [Conf]
  49. Jui-Hua Li, Nam Ling
    An efficient video decoder design for MPEG-2 MP@ML. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:509-518 [Conf]
  50. Christian Luetkemeyer
    An Optimized Coefficient Update Processor for High-Throughput Adaptive Equalizers. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:519-528 [Conf]
  51. Benjamin W. Wah, Yi Shang, Zhe Wu
    Discrete Lagrangian Method for Optimizing the Design of Multiplierless QMF Filter Banks. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:529-0 [Conf]
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