Conferences in DBLP
William S. Song High-Performance Front-End Embedded Signal Processors for Adaptive Sensor Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Ruby B. Lee Subword Permutation Instructions for Two-Dimensional Multimedia Processing in MicroSIMD Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Mladen Berekovic , Peter Pirsch , Thorsten Selinger , Kai-Immo Wels , Carolina Miro , Anne Lafage , Christoph Heer , Giovanni Ghigo Architecture of an Image Rendering Co-Processor for MPEG-4 Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Wael M. Badawy , Magdy A. Bayoumi A Multiplication-Free Parallel Architecture for Affine Transformation. [Citation Graph (0, 0)][DBLP ] Conf ] Marco Antonio Dal Poz , J. Aedo Cobo , Wilhelmus A. M. Van Noije , Marcelo Knörich Zuffo A Simple RISC Microprocessor Core Designed for Digital Set-Top-Box Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Sergej Sawitzki , Rainer G. Spallek , Jens Schönherr , Bernd Straube Formal Verification for Microprocessors with Extendable Instruction Set. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Rinker , Jeffrey Hammes , Walid A. Najjar , A. P. Wim Böhm , Bruce A. Draper Compiling Image Processing Applications to Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Holger Blume , Hans-Martin Blüthgen , Christiane Henning , Patrick Osterloh Integration of High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality. [Citation Graph (0, 0)][DBLP ] Conf ] Ed F. Deprettere , Edwin Rijpkema , Paul Lieverse , Bart Kienhuis High Level Modeling for Parallel Executions of Nested Loop Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew Stone , Elias S. Manolakos Minimal Complexity Hierarchical Loop Representations of SFG Processors for Optimal High Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Tsong Shiue High Level Synthesis for Peak Power Minimization Using ILP. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Schreiber , Shail Aditya , B. Ramakrishna Rau , Vinod Kathail , Scott A. Mahlke , Santosh G. Abraham , Greg Snider High-Level Synthesis of Nonprogrammable Hardware Accelerators. [Citation Graph (0, 0)][DBLP ] Conf ] B. J. Phillips , N. Burgess Implementing 1, 024-Bit RSA Exponentiation on a 32-Bit Processor Core. [Citation Graph (0, 0)][DBLP ] Conf ] Zhijie Shi , Ruby B. Lee Bit Permutation Instructions for Accelerating Software Cryptography. [Citation Graph (0, 0)][DBLP ] Conf ] William L. Freking , Keshab K. Parhi Performance-Scalable Array Architectures for Modular Multiplication. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmed M. Shams , Magdy A. Bayoumi A 108 Gbps, 1.5 GHz 1D-DCT Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Sridhar Rajagopal , Srikrishna Bhashyam , Joseph R. Cavallaro , Behnaam Aazhang Efficient VLSI Architectures for Baseband Signal Processing in Wireless Base-Station Receivers. [Citation Graph (0, 0)][DBLP ] Conf ] Naraig Manjikian A Vector Multiprocessor for Real-Time Multi-User Detection in Spread-Spectrum Communication. [Citation Graph (0, 0)][DBLP ] Conf ] V. S. Gierenz , Oliver Weiss , Tobias G. Noll , I. Carew , J. Ashley , R. Karabed A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-mu m CMOS Viterbi Decoder. [Citation Graph (0, 0)][DBLP ] Conf ] Marc Daumas , David W. Matula A Booth Multiplier Accepting Both a Redundant or a Non-Redundant Input with No Additional Delay. [Citation Graph (0, 0)][DBLP ] Conf ] Javier Hormigo , Julio Villalba , Michael J. Schulte A Hardware Algorithm for Variable-Precision Logarithm. [Citation Graph (0, 0)][DBLP ] Conf ] Lijun Gao , Keshab K. Parhi Block-Update Parallel Processing QRD-RLS Algorithm for Throughput Improvement with Low Power Consumption. [Citation Graph (0, 0)][DBLP ] Conf ] Ohsang Kwon , Earl E. Swartzlander Jr. , Kevin J. Nowka A 16-Bit x 16-Bit MAC Design Using Fast 5: 2 Compressors. [Citation Graph (0, 0)][DBLP ] Conf ] Martin C. Herbordt , Honghai Zhang , Calvin Lin , Hong Rao , Jade Cravy Control for High-Speed PE Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Andrea Di Blas , Richard Hughey Explicit SIMD Programming for Asynchronous Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Scott Bowden , Doran Wilde , Sanjay V. Rajopadhye Quadratic Control Signals in Linear Systolic Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Mukul Khandelia , Shuvra S. Bhattacharyya Contention-Conscious Transaction Ordering in Embedded Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] María A. Trenas , Juan López , Manuel Sánchez , Emilio L. Zapata , Francisco Argüello Architecture for Wavelet Packet Transform with Best Tree Searching. [Citation Graph (0, 0)][DBLP ] Conf ] Marcus Bednara , Oliver Beyer , Jürgen Teich , Rolf Wanka Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter. [Citation Graph (0, 0)][DBLP ] Conf ] Hans-Martin Blüthgen , Tobias G. Noll A Programmable Processor for Approximate String Matching with High Throughput Rate. [Citation Graph (0, 0)][DBLP ] Conf ] H. Safiri , Majid Ahmadi , Graham A. Jullien , William C. Miller A New Algorithm for the Elimination of Common Subexpressions in Hardware Implementation of Digital Filters by Using Genetic Programming. [Citation Graph (0, 0)][DBLP ] Conf ] Ramaswamy Govindarajan , Erik R. Altman , Guang R. Gao A Theory for Software-Hardware Co-Scheduling for ASIPs and Embedded Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Auguin , Luc Bianco , L. Capella , Emmanuel Gresset Partitioning Conditional Data Flow Graphs for Embedded System Design. [Citation Graph (0, 0)][DBLP ] Conf ] Dirk Fimmel Generation of Scheduling Functions Supporting LSGP-Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] 