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Conferences in DBLP

Application-Specific Systems, Architectures, and Processors (asap)
2000 (conf/asap/2000)

  1. William S. Song
    High-Performance Front-End Embedded Signal Processors for Adaptive Sensor Arrays. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:- [Conf]
  2. Ruby B. Lee
    Subword Permutation Instructions for Two-Dimensional Multimedia Processing in MicroSIMD Architectures. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:3-14 [Conf]
  3. Mladen Berekovic, Peter Pirsch, Thorsten Selinger, Kai-Immo Wels, Carolina Miro, Anne Lafage, Christoph Heer, Giovanni Ghigo
    Architecture of an Image Rendering Co-Processor for MPEG-4 Systems. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:15-24 [Conf]
  4. Wael M. Badawy, Magdy A. Bayoumi
    A Multiplication-Free Parallel Architecture for Affine Transformation. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:25-34 [Conf]
  5. Marco Antonio Dal Poz, J. Aedo Cobo, Wilhelmus A. M. Van Noije, Marcelo Knörich Zuffo
    A Simple RISC Microprocessor Core Designed for Digital Set-Top-Box Applications. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:35-0 [Conf]
  6. Sergej Sawitzki, Rainer G. Spallek, Jens Schönherr, Bernd Straube
    Formal Verification for Microprocessors with Extendable Instruction Set. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:47-55 [Conf]
  7. Robert Rinker, Jeffrey Hammes, Walid A. Najjar, A. P. Wim Böhm, Bruce A. Draper
    Compiling Image Processing Applications to Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:56-65 [Conf]
  8. Holger Blume, Hans-Martin Blüthgen, Christiane Henning, Patrick Osterloh
    Integration of High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:66-0 [Conf]
  9. Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, Bart Kienhuis
    High Level Modeling for Parallel Executions of Nested Loop Algorithms. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:79-91 [Conf]
  10. Andrew Stone, Elias S. Manolakos
    Minimal Complexity Hierarchical Loop Representations of SFG Processors for Optimal High Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:92-102 [Conf]
  11. Wen-Tsong Shiue
    High Level Synthesis for Peak Power Minimization Using ILP. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:103-112 [Conf]
  12. Robert Schreiber, Shail Aditya, B. Ramakrishna Rau, Vinod Kathail, Scott A. Mahlke, Santosh G. Abraham, Greg Snider
    High-Level Synthesis of Nonprogrammable Hardware Accelerators. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:113-0 [Conf]
  13. B. J. Phillips, N. Burgess
    Implementing 1, 024-Bit RSA Exponentiation on a 32-Bit Processor Core. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:127-137 [Conf]
  14. Zhijie Shi, Ruby B. Lee
    Bit Permutation Instructions for Accelerating Software Cryptography. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:138-148 [Conf]
  15. William L. Freking, Keshab K. Parhi
    Performance-Scalable Array Architectures for Modular Multiplication. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:149-0 [Conf]
  16. Ahmed M. Shams, Magdy A. Bayoumi
    A 108 Gbps, 1.5 GHz 1D-DCT Architecture. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:163-172 [Conf]
  17. Sridhar Rajagopal, Srikrishna Bhashyam, Joseph R. Cavallaro, Behnaam Aazhang
    Efficient VLSI Architectures for Baseband Signal Processing in Wireless Base-Station Receivers. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:173-184 [Conf]
  18. Naraig Manjikian
    A Vector Multiprocessor for Real-Time Multi-User Detection in Spread-Spectrum Communication. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:185-194 [Conf]
  19. V. S. Gierenz, Oliver Weiss, Tobias G. Noll, I. Carew, J. Ashley, R. Karabed
    A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-mu m CMOS Viterbi Decoder. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:195-0 [Conf]
  20. Marc Daumas, David W. Matula
    A Booth Multiplier Accepting Both a Redundant or a Non-Redundant Input with No Additional Delay. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:205-214 [Conf]
  21. Javier Hormigo, Julio Villalba, Michael J. Schulte
    A Hardware Algorithm for Variable-Precision Logarithm. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:215-224 [Conf]
  22. Lijun Gao, Keshab K. Parhi
    Block-Update Parallel Processing QRD-RLS Algorithm for Throughput Improvement with Low Power Consumption. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:225-234 [Conf]
  23. Ohsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka
    A 16-Bit x 16-Bit MAC Design Using Fast 5: 2 Compressors. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:235-0 [Conf]
  24. Martin C. Herbordt, Honghai Zhang, Calvin Lin, Hong Rao, Jade Cravy
    Control for High-Speed PE Arrays. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:247-257 [Conf]
  25. Andrea Di Blas, Richard Hughey
    Explicit SIMD Programming for Asynchronous Applications. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:258-267 [Conf]
  26. Scott Bowden, Doran Wilde, Sanjay V. Rajopadhye
    Quadratic Control Signals in Linear Systolic Arrays. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:268-275 [Conf]
  27. Mukul Khandelia, Shuvra S. Bhattacharyya
    Contention-Conscious Transaction Ordering in Embedded Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:276-0 [Conf]
  28. María A. Trenas, Juan López, Manuel Sánchez, Emilio L. Zapata, Francisco Argüello
    Architecture for Wavelet Packet Transform with Best Tree Searching. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:289-298 [Conf]
  29. Marcus Bednara, Oliver Beyer, Jürgen Teich, Rolf Wanka
    Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:299-308 [Conf]
  30. Hans-Martin Blüthgen, Tobias G. Noll
    A Programmable Processor for Approximate String Matching with High Throughput Rate. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:309-0 [Conf]
  31. H. Safiri, Majid Ahmadi, Graham A. Jullien, William C. Miller
    A New Algorithm for the Elimination of Common Subexpressions in Hardware Implementation of Digital Filters by Using Genetic Programming. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:319-328 [Conf]
  32. Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao
    A Theory for Software-Hardware Co-Scheduling for ASIPs and Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:329-338 [Conf]
  33. Michel Auguin, Luc Bianco, L. Capella, Emmanuel Gresset
    Partitioning Conditional Data Flow Graphs for Embedded System Design. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:339-348 [Conf]
  34. Dirk Fimmel
    Generation of Scheduling Functions Supporting LSGP-Partitioning. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:349-0 [Conf]
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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002