|
|
Conferences in DBLP
- José A. B. Fortes
Nanocomputing with Delays. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:3-0 [Conf]
- Manju Manjunathaiah, Graham M. Megson
Compositional Technique for Synthesising Multi-Phase Regular Arrays. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:7-16 [Conf]
- Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
A Compile Time Based Approach for Solving Out-of-Order Communication in Kahn Process Networks. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:17-28 [Conf]
- Holger Blume, H. Hübert, H. T. Feldkämper, Tobias G. Noll
Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:29-40 [Conf]
- Gary Spivey, Shuvra S. Bhattacharyya, Kazuo Nakajima
A Component Architecture for FPGA-Based, DSP System Design. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:41-0 [Conf]
- Wen-Tsong Shiue
Low Power Memory Design. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:55-64 [Conf]
- Mark G. Arnold
Reduced Power Consumption for MPEG Decoding with LNS. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:65-75 [Conf]
- Sumit Mohanty, Seonil Choi, Ju-wook Jang, Viktor K. Prasanna
A Model-Based Methodology for Application Specific Energy Efficient Data Path Design Using FPGAs. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:76-87 [Conf]
- Lin Yuan, Gang Qu
Design Space Exploration for Energy-Efficient Secure Sensor Network. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:88-0 [Conf]
- José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera
High-Radix Logarithm with Selection by Rounding. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:101-110 [Conf]
- Chang Yong Kang, Earl E. Swartzlander Jr.
An Analysis of the CORDIC Algorithm for Direct Digital Frequency Synthesis. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:111-119 [Conf]
- David W. Matula, Alex Fit-Florea, Lee D. McFearin
Evaluating Products of Non Linear Functions by Indirect Bipartite Table Lookup. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:120-129 [Conf]
- Roberto Muscedere, Vassil S. Dimitrov, Graham A. Jullien, William C. Miller
Efficient Conversion From Binary to Multi-Digit Multi-Dimensional Logarithmic Number Systems Using Arrays of Range Addressable Look-Up Tables. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:130-0 [Conf]
- James Irwin, David May, Henk L. Muller, Dan Page
Predictable Instruction Caching for Media Processors. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:141-150 [Conf]
- Afzal Hossain, Daniel J. Pease, James S. Burns, Nasima Parveen
A Mathematical Model of Trace Cache. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:151-162 [Conf]
- Jeffrey T. Draper, Jeff Sondeen, Sumit D. Mediratta, Ihn Kim
Implementation of a 32-bit RISC Processor for the Data-Intensive Architecture Processing-In-Memory Chip. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:163-172 [Conf]
- Woo-Chan Park, Kil-Whan Lee, Il-San Kim, Tack-Don Han, Sung-Bong Yang
A Mid-Texturing Pixel Rasterization Pipeline Architecture for 3D Rendering Processors. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:173-0 [Conf]
- Elisardo Antelo, Tomás Lang, Paolo Montuschi, Alberto Nannarelli
Fast Radix-4 Retimed Division with Selection by Comparisons. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:185-196 [Conf]
- Neil Burgess
PAPA - Packed Arithmetic on a Prefix Adder for Multimedia Applications. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:197-207 [Conf]
- Ahmet Akkas
A Combined Interval and Floating-Point Comparator/Selector. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:208-217 [Conf]
- Peter Kornerup
Reviewing 4-to-2 Adders for Multi-Operand Addition. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:218-0 [Conf]
- Byeong Kil Lee, Lizy Kurian John
Implications of Programmable General Purpose Processors for Compression/Encryption Applications. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:233-242 [Conf]
- Chris Y. Chung, Ravi Managuli, Yongmin Kim
Design and Evaluation of a Multimedia Computing Architecture Based on a 3D Graphics Pipeline. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:243-252 [Conf]
- Ruby B. Lee, A. Murat Fiskiran, Zhijie Shi, Xiao Yang
Refining Instruction Set Architecture for High-Performance Multimedia Processing in Constrained Environments. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:253-264 [Conf]
- Julio Villalba, Gerardo Bandera, Mario A. González, Javier Hormigo, Emilio L. Zapata
Polynomial Evaluation on Multimedia Processors. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:265-0 [Conf]
- Chih-Chung Lu, Shau-Yin Tseng
Integrated Design of AES (Advanced Encryption Standard) Encrypter and Decrypter. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:277-285 [Conf]
- James Irwin, Dan Page, Nigel P. Smart
Instruction Stream Mutation for Non-Deterministic Processors. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:286-295 [Conf]
- Mehboob Alam, Wael M. Badawy, Graham A. Jullien
A Novel Pipelined Threads Architecture for AES Encryption Algorithm. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:296-302 [Conf]
- Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri
On the Propagation of Faults and Their Detection in a Hardware Implementation of the Advanced Encryption Standard. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:303-0 [Conf]
- E. I. Chester, J. N. Coleman
Matrix Engine for Signal Processing Applications Using the Logarithmic Number System. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:315-324 [Conf]
- K. Sitaraman, N. Ranganathan, Abdel Ejnioui
A VLSI Architecture for Object Recognition Using Tree Matching. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:325-334 [Conf]
- Steven M. Currie, Paul R. Schumacher, Barry K. Gilbert, Earl E. Swartzlander Jr., Barbara A. Randall
Implementation of a Single Chip, Pipelined, Complex, One-Dimensional Fast FourierTransform in 0.25 mu m BulkCMOS. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:335-343 [Conf]
- Roger D. Chamberlain, Mark A. Franklin, Praveen Krishnamurthy
Optical Network Reconfiguration for Signal Processing Applications. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:344-0 [Conf]
- Alain Darte, Guillaume Huard
New Results on Array Contraction. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:359-370 [Conf]
- Tsai-Yun Liao, Ta-Yin Hu
A CORBA-Based GIS-T for Ambulance Assignment. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:371-380 [Conf]
- David Cachera, Tanguy Risset
Advances in Bit Width Selection Methodology. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:381-390 [Conf]
- Michael D. DeVore, Roger D. Chamberlain, George Engel, Joseph A. O'Sullivan, Mark A. Franklin
Tradeoffs Between Quality of Results and Resource Consumption in a Recognition System. [Citation Graph (0, 0)][DBLP]
ASAP, 2002, pp:391-0 [Conf]
|
