Conferences in DBLP
François Charot , Madeleine Nyamsi , Patrice Quinton , Charles Wagner Modeling and Scheduling Parallel Data Flow Systems using Structured Systems of Recurrence Equations. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Hannig , Jürgen Teich Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals. [Citation Graph (0, 0)][DBLP ] Conf ] Vida Kianzad , Shuvra S. Bhattacharyya CHARMED: A Multi-Objective Co-Synthesis Framework for Multi-Mode Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Yuan Xie , Lin Li , Mahmut T. Kandemir , Narayanan Vijaykrishnan , Mary Jane Irwin Reliability-Aware Co-Synthesis for Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Milos D. Ercegovac , Jean-Michel Muller Complex Square Root with Operand Prescaling. [Citation Graph (0, 0)][DBLP ] Conf ] Moboluwaji O. Sanu , Earl E. Swartzlander Jr. , Craig M. Chase Parallel Montgomery Multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Alexandre F. Tenca , Ajay C. Shantilal , Mohammed H. Sinky Improved-Throughput Networks of Basic On-Line Arithmetic Modules for DSP Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Liang-Kai Wang , Michael J. Schulte Decimal Floating-Point Division Using Newton-Raphson Iteration. [Citation Graph (0, 0)][DBLP ] Conf ] Hans Eberle , Nils Gura , Sheueling Chang Shantz , Vipul Gupta , Leonard Rarick , Shreyas Sundaram A Public-Key Cryptographic Processor for RSA and ECC. [Citation Graph (0, 0)][DBLP ] Conf ] Johann Großschädl , Sandeep S. Kumar , Christof Paar Architectural Support for Arithmetic in Optimal Extension Fields. [Citation Graph (0, 0)][DBLP ] Conf ] A. Murat Fiskiran , Ruby B. Lee Evaluating Instruction Set Extensions for Fast Arithmetic on Binary Finite Fields. [Citation Graph (0, 0)][DBLP ] Conf ] Jongmyon Kim , D. Scott Wills Efficient Processing of Color Image Sequences Using a Color-Aware Instruction Set on Mobile Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Casper Lageweg , Sorin Cotofana , Stamatis Vassiliadis Binary Multiplication based on Single Electron Tunneling. [Citation Graph (0, 0)][DBLP ] Conf ] Valeriu Beiu A Novel Highly Reliable Low-Power Nano Architecture When von Neumann Augments. [Citation Graph (0, 0)][DBLP ] Conf ] Rama Sangireddy Register Organization for Enhanced On-Chip Parallelism. [Citation Graph (0, 0)][DBLP ] Conf ] Ljiljana Dilparic , D. K. Arvind Design and Evaluation of a Network-Based Asynchronous Architecture for Cryptographic Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Anup Hosangadi , Farzan Fallah , Ryan Kastner Common Subexpression Elimination Involving Multiple Variables for Linear DSP Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] José Ignacio Gómez , Paul Marchal , Sven Verdoolaege , Luis Piñuel , Francky Catthoor Optimizing the Memory Bandwidth with Loop Morphing. [Citation Graph (0, 0)][DBLP ] Conf ] Zili Shao , Qingfeng Zhuge , Meilin Liu , Bin Xiao , Edwin Hsing-Mean Sha Switching-Activity Minimization on Instruction-Level Loop Scheduling for VLIWDSP Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Alex Fit-Florea , David W. Matula A Digit-Serial Algorithm for the Discrete Logarithm Modulo 2k . [Citation Graph (0, 0)][DBLP ] Conf ] Lo'ai A. Tawalbeh , Alexandre F. Tenca An Algorithm and Hardware Architecture for Integrated Modular Division and Multiplication in GF(p) and GF(2n ). [Citation Graph (0, 0)][DBLP ] Conf ] Luca Breveglieri , Israel Koren , Paolo Maistri Detecting Faults in Four Symmetric Key Block Ciphers. [Citation Graph (0, 0)][DBLP ] Conf ] Michael J. Schulte , Kai Chirca , John Glossner , Haoran Wang , Suman Mamidi , Pablo I. Balzola , Stamatis Vassiliadis A Low-Power Carry Skip Adder with Fast Saturation. [Citation Graph (0, 0)][DBLP ] Conf ] Alexandru Turjan , Bart Kienhuis , Ed F. Deprettere A Hierarchical Classification Scheme to Derive Interprocess Communication in Process Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Antoine Fraboulet , Tanguy Risset Efficient On-Chip Communications for Data-Flow IPs. [Citation Graph (0, 0)][DBLP ] Conf ] Manjunath Kudlur , Kevin Fan , Michael L. Chu , Scott A. Mahlke Automatic Synthesis of Customized Local Memories for Multicluster Application Accelerators. [Citation Graph (0, 0)][DBLP ] Conf ] Sebastian Siegel , Renate Merker Optimized Data-Reuse in Processor Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Gordon J. Brebner , Philip James-Roxby , Eric Keller , Chidamber Kulkarni Hyper-Programmable Architectures for Adaptable Networked Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Miljan Vuletic , Laura Pozzi , Paolo Ienne Programming Transparency and Portable Hardware Interfacing: Towards General-Purpose Reconfigurable Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Van Court , Martin C. Herbordt Families of FPGA-Based Algorithms for Approximate String Matching. [Citation Graph (0, 0)][DBLP ] Conf ] Praveen Krishnamurthy , Jeremy Buhler , Roger D. Chamberlain , Mark A. Franklin , Kwame Gyang , Joseph M. Lancaster Biosequence Similarity Search on the Mercury System. [Citation Graph (0, 0)][DBLP ] Conf ] Tuomas Järvinen , Perttu Salmela , Harri Sorokin , Jarmo Takala Stride Permutation Networks for Array Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Fabien Castanier , Alberto Ferrante , Vincenzo Piuri A Packet Scheduling Algorithm for IPSec Multi-Accelerator Based Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Oliver Amft , Michael Lauffer , Stijn Ossevoort , Fabrizio Macaluso , Paul Lukowicz , Gerhard Tröster Design of the QBIC Wearable Computing Platform. [Citation Graph (0, 0)][DBLP ] Conf ] 