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Conferences in DBLP

Application-Specific Systems, Architectures, and Processors (asap)
2004 (conf/asap/2004)

  1. François Charot, Madeleine Nyamsi, Patrice Quinton, Charles Wagner
    Modeling and Scheduling Parallel Data Flow Systems using Structured Systems of Recurrence Equations. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:6-16 [Conf]
  2. Frank Hannig, Jürgen Teich
    Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:17-27 [Conf]
  3. Vida Kianzad, Shuvra S. Bhattacharyya
    CHARMED: A Multi-Objective Co-Synthesis Framework for Multi-Mode Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:28-40 [Conf]
  4. Yuan Xie, Lin Li, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
    Reliability-Aware Co-Synthesis for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:41-50 [Conf]
  5. Milos D. Ercegovac, Jean-Michel Muller
    Complex Square Root with Operand Prescaling. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:52-62 [Conf]
  6. Moboluwaji O. Sanu, Earl E. Swartzlander Jr., Craig M. Chase
    Parallel Montgomery Multipliers. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:63-72 [Conf]
  7. Alexandre F. Tenca, Ajay C. Shantilal, Mohammed H. Sinky
    Improved-Throughput Networks of Basic On-Line Arithmetic Modules for DSP Applications. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:73-83 [Conf]
  8. Liang-Kai Wang, Michael J. Schulte
    Decimal Floating-Point Division Using Newton-Raphson Iteration. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:84-95 [Conf]
  9. Hans Eberle, Nils Gura, Sheueling Chang Shantz, Vipul Gupta, Leonard Rarick, Shreyas Sundaram
    A Public-Key Cryptographic Processor for RSA and ECC. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:98-110 [Conf]
  10. Johann Großschädl, Sandeep S. Kumar, Christof Paar
    Architectural Support for Arithmetic in Optimal Extension Fields. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:111-124 [Conf]
  11. A. Murat Fiskiran, Ruby B. Lee
    Evaluating Instruction Set Extensions for Fast Arithmetic on Binary Finite Fields. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:125-136 [Conf]
  12. Jongmyon Kim, D. Scott Wills
    Efficient Processing of Color Image Sequences Using a Color-Aware Instruction Set on Mobile Systems. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:137-149 [Conf]
  13. Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis
    Binary Multiplication based on Single Electron Tunneling. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:152-166 [Conf]
  14. Valeriu Beiu
    A Novel Highly Reliable Low-Power Nano Architecture When von Neumann Augments. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:167-177 [Conf]
  15. Rama Sangireddy
    Register Organization for Enhanced On-Chip Parallelism. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:180-190 [Conf]
  16. Ljiljana Dilparic, D. K. Arvind
    Design and Evaluation of a Network-Based Asynchronous Architecture for Cryptographic Devices. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:191-201 [Conf]
  17. Anup Hosangadi, Farzan Fallah, Ryan Kastner
    Common Subexpression Elimination Involving Multiple Variables for Linear DSP Synthesis. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:202-212 [Conf]
  18. José Ignacio Gómez, Paul Marchal, Sven Verdoolaege, Luis Piñuel, Francky Catthoor
    Optimizing the Memory Bandwidth with Loop Morphing. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:213-223 [Conf]
  19. Zili Shao, Qingfeng Zhuge, Meilin Liu, Bin Xiao, Edwin Hsing-Mean Sha
    Switching-Activity Minimization on Instruction-Level Loop Scheduling for VLIWDSP Applications. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:224-234 [Conf]
  20. Alex Fit-Florea, David W. Matula
    A Digit-Serial Algorithm for the Discrete Logarithm Modulo 2k. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:236-246 [Conf]
  21. Lo'ai A. Tawalbeh, Alexandre F. Tenca
    An Algorithm and Hardware Architecture for Integrated Modular Division and Multiplication in GF(p) and GF(2n). [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:247-257 [Conf]
  22. Luca Breveglieri, Israel Koren, Paolo Maistri
    Detecting Faults in Four Symmetric Key Block Ciphers. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:258-268 [Conf]
  23. Michael J. Schulte, Kai Chirca, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis
    A Low-Power Carry Skip Adder with Fast Saturation. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:269-279 [Conf]
  24. Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
    A Hierarchical Classification Scheme to Derive Interprocess Communication in Process Networks. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:282-292 [Conf]
  25. Antoine Fraboulet, Tanguy Risset
    Efficient On-Chip Communications for Data-Flow IPs. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:293-303 [Conf]
  26. Manjunath Kudlur, Kevin Fan, Michael L. Chu, Scott A. Mahlke
    Automatic Synthesis of Customized Local Memories for Multicluster Application Accelerators. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:304-314 [Conf]
  27. Sebastian Siegel, Renate Merker
    Optimized Data-Reuse in Processor Arrays. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:315-325 [Conf]
  28. Gordon J. Brebner, Philip James-Roxby, Eric Keller, Chidamber Kulkarni
    Hyper-Programmable Architectures for Adaptable Networked Systems. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:328-338 [Conf]
  29. Miljan Vuletic, Laura Pozzi, Paolo Ienne
    Programming Transparency and Portable Hardware Interfacing: Towards General-Purpose Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:339-351 [Conf]
  30. Tom Van Court, Martin C. Herbordt
    Families of FPGA-Based Algorithms for Approximate String Matching. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:354-364 [Conf]
  31. Praveen Krishnamurthy, Jeremy Buhler, Roger D. Chamberlain, Mark A. Franklin, Kwame Gyang, Joseph M. Lancaster
    Biosequence Similarity Search on the Mercury System. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:365-375 [Conf]
  32. Tuomas Järvinen, Perttu Salmela, Harri Sorokin, Jarmo Takala
    Stride Permutation Networks for Array Processors. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:376-386 [Conf]
  33. Fabien Castanier, Alberto Ferrante, Vincenzo Piuri
    A Packet Scheduling Algorithm for IPSec Multi-Accelerator Based Systems. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:387-397 [Conf]
  34. Oliver Amft, Michael Lauffer, Stijn Ossevoort, Fabrizio Macaluso, Paul Lukowicz, Gerhard Tröster
    Design of the QBIC Wearable Computing Platform. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:398-410 [Conf]
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