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Conferences in DBLP

Asia-Pacific Computer Systems Architecture Conference (ACSAC) (aPcsac)
2000 (conf/aPcsac/2000)

  1. Hon Nin Cheung, Li-minn Ang, Kamran Eshraghian
    Parallel Architecture for the Implementation of the Embedded Zerotree Wavelet Algorithm. [Citation Graph (0, 0)][DBLP]
    ACAC, 2000, pp:3-8 [Conf]
  2. Wanming Chu, Yamin Li
    Cost/Performance Tradeoff of n-Select Square Root Implementations. [Citation Graph (0, 0)][DBLP]
    ACAC, 2000, pp:9-16 [Conf]
  3. Lieven Eeckhout, Koen De Bosschere, Henk Neefs
    On the Feasibility of Fixed-Length Block Structured Architectures. [Citation Graph (0, 0)][DBLP]
    ACAC, 2000, pp:17-25 [Conf]
  4. Bernard K. Gunther
    The Circuit Object Organization Library. [Citation Graph (0, 0)][DBLP]
    ACAC, 2000, pp:26-33 [Conf]
  5. Chris R. Jesshope, Bing Luo
    Micro-Threading: A New Approach to Future RISC. [Citation Graph (0, 0)][DBLP]
    ACAC, 2000, pp:34-41 [Conf]
  6. Gareth Lee, John Morris
    Dataflow Java: Implicitly Parallel Java. [Citation Graph (0, 0)][DBLP]
    ACAC, 2000, pp:42-50 [Conf]
  7. T. Lund, Antonio B. Torralba, Ramón González Carvajal
    The Architecture of an FPGA-Style Programmable Fuzzy Logic Controller Chip. [Citation Graph (0, 0)][DBLP]
    ACAC, 2000, pp:51-56 [Conf]
  8. Bruce McClure, T. A. Au, Jadwiga Indulska
    Adaptive Middleware for Heterogeneous Defense Networks-An Exploratory Simulation Study. [Citation Graph (0, 0)][DBLP]
    ACAC, 2000, pp:57-63 [Conf]
  9. John Morris, Gary A. Bundell, Sonny Tham
    A Scalable Re-Configurable Processor. [Citation Graph (0, 0)][DBLP]
    ACAC, 2000, pp:64-73 [Conf]
  10. Partha S. Roop, Arcot Sowmya, S. Ramesh
    Automated Component Adaptation by Forced Simulation. [Citation Graph (0, 0)][DBLP]
    ACAC, 2000, pp:74-81 [Conf]
  11. Christian Siemers, Sybille Siemers
    Reconfigurable Computing Based on Universal Configurable Blocks-A New Approach for Supporting Performance- and Realtime-Dominated Applications. [Citation Graph (0, 0)][DBLP]
    ACAC, 2000, pp:82-89 [Conf]
  12. Daniel Tate, Gordon Steven, Fleur Steven
    Static Scheduling for Out-of-order Instruction Issue Processors. [Citation Graph (0, 0)][DBLP]
    ACAC, 2000, pp:90-96 [Conf]
  13. Adam Wiggins, Gernot Heiser
    Fast Address-Space Switching on the StrongARM SA-1100 Processor. [Citation Graph (0, 0)][DBLP]
    ACAC, 2000, pp:97-0 [Conf]
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