The SCEAS System
Navigation Menu

Conferences in DBLP

Asia-Pacific Computer Systems Architecture Conference (ACSAC) (aPcsac)
2003 (conf/aPcsac/2003)

  1. Tetsuya Sato, Hitoshi Murai, Shigemune Kitawaki
    How Can the Earth Simulator Impact on Human Activities. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:1-7 [Conf]
  2. Tadao Nakamura
    Toward Architecting and Designing Novel Computers. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:8-13 [Conf]
  3. Doug Burger
    Designing Ultra-large Instruction Issue Windows. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:14-20 [Conf]
  4. Chris R. Jesshope
    Multi-threaded Microprocessors - Evolution or Revolution. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:21-45 [Conf]
  5. Victor Korneev
    The Development of System Software for Parallel Supercomputers. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:46-53 [Conf]
  6. Kiyoshi Oguri, Yuichiro Shibata, Akira Nagoya
    Asynchronous Bit-Serial Datapath for Object-Oriented Reconfigurable Architecture PCA. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:54-68 [Conf]
  7. John Morris
    Reconfigurable Logic: A Saviour for Experimental Computer Architecture Research. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:69-85 [Conf]
  8. Amos Omondi
    Design and Implementation of Java Processors. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:86-96 [Conf]
  9. Radim Ballner, Pavel Tvrdík
    MOOSS: CPU Architecture with Memory Protection and Support for OOP. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:97-111 [Conf]
  10. Hiroshi Takamura, Koji Inoue, Vasily G. Moshnyaga
    Reducing Access Count to Register-Files through Operand Reuse. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:112-121 [Conf]
  11. Kenji Kise, Hiroki Honda, Toshitsugu Yuba
    SimAlpha Version 1.0: Simple and Readable Alpha Processor Simulator. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:122-136 [Conf]
  12. Qianyi Zhang, Georgios K. Theodoropoulos
    Towards an Asynchronous MIPS Processor. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:137-150 [Conf]
  13. G. Stewart Von Itzstein, Mark Jasiunas
    On Implementing High Level Concurrency in Java. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:151-165 [Conf]
  14. H. Pradeep Rao, S. K. Nandy, M. N. V. Satya Kiran
    Simultaneous MultiStreaming for Complexity-Effective VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:166-179 [Conf]
  15. Paul Gardner-Stephen, Greg Knowles
    A Novel Architecture for Genomic Sequence Searching and Alignment. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:180-192 [Conf]
  16. Sebastian Wallner
    A Reconfigurable Multi-threaded Architecture Model. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:193-207 [Conf]
  17. Toshiyuki Ito, Kentaro Ono, Mayumi Ichikawa, Yuichi Okuyama, Kenichi Kuroda
    Reconfigurable Instruction-Level Parallel Processor Architecture. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:208-220 [Conf]
  18. Yuanqing Guo, Gerard J. M. Smit, Hajo Broersma, Michèl A. J. Rosien, Paul M. Heysters
    Mapping Applications to a Coarse Grain Reconfigurable System. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:221-235 [Conf]
  19. Abhinandan Sharma, Martyn A. George, David A. Kearney
    Packing with Boundary Constraints for a Reconfigurable Operating System. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:236-245 [Conf]
  20. Anders Lindström, Michael Nordseth, Lars Bengtsson, Amos Omondi
    Arithmetic Circuits Combining Residue and Signed-Digit Representations. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:246-257 [Conf]
  21. Hooman Nikmehr, Cheng-Chew Lim
    A New On-the-fly Summation Algorithm. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:258-267 [Conf]
  22. Kun-Lin Tsai, Feipei Lai, Shanq-Jang Ruan, Szu-Wei Chaung
    State Reordering for Low Power Combinational Logic. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:268-276 [Conf]
  23. Andreas Haeberlen, Kevin Elphinstone
    User-Level Management of Kernel Memory. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:277-289 [Conf]
  24. Cristan Szmajda, Gernot Heiser
    Variable Radix Page Table: A Page Table for Modern Architectures. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:290-304 [Conf]
  25. Philip Machanick, Zunaid Patel
    L1 Cache and TLB Enhancements to the RAMpage Memory Hierarchy. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:305-319 [Conf]
  26. Adam Wiggins, Simon Winwood, Harvey Tuch, Gernot Heiser
    Legba: Fast Hardware Support for Fine-Grained Protection. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:320-336 [Conf]
  27. Mohan G. Kabadi, Ranjani Parthasarathi
    Live-Cache: Exploiting Data Redundancy to Reduce Leakage Energy in a Cache Subsystem. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:337-351 [Conf]
  28. Adam Wiggins, Harvey Tuch, Volkmar Uhlig, Gernot Heiser
    Implementation of Fast Address-Space Switching and TLB Sharing on the StrongARM Processor. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:352-364 [Conf]
  29. Sonny Tham, John Morris
    Performance of the Achilles Router. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:365-379 [Conf]
  30. Philip Machanick, Brynn Andrew
    Latency Improvement in Virtual Multicasting. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:380-394 [Conf]
  31. Muhammad Mahmudul Islam, Ronald Pose, Carlo Kopp
    A Router Architecture to Achieve Link Rate Throughput in Suburban Ad-hoc Networks. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2003, pp:395-407 [Conf]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002