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Conferences in DBLP
(recosoc)
2005 (conf/recosoc/2005)
- Andreas Koch, Nico Kasprzyk
High-Level-Language Compilation for Reconfigurable Computers. [Citation Graph (0, 0)][DBLP]
ReCoSoC, 2005, pp:1-8 [Conf]
- Yves Lhuillier, Pierre Palatin, Olivier Temam
Symbiotic Processing: Toward a Better Balance Between Architecture, Compiler and User Efforts. [Citation Graph (0, 0)][DBLP]
ReCoSoC, 2005, pp:9-18 [Conf]
- Christophe Gouyen, Loïc Lagadec, Bernard Pottier, A. André, E. Lepicier, François Dupont
Compiler level integration of a portable CAD framework for reconfigurable circuits. [Citation Graph (0, 0)][DBLP]
ReCoSoC, 2005, pp:19-26 [Conf]
- Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Menard, Olivier Sentieys
Co-Design of Massively Parallel Embedded Processor Architectures. [Citation Graph (0, 0)][DBLP]
ReCoSoC, 2005, pp:27-34 [Conf]
- Jürgen Becker, Michael Hübner, Katarina Paulsson, Alexander Thomas
Dynamic Reconfiguration On-Demand: Real-time Adaptivity in Next Generation Microelectronics. [Citation Graph (0, 0)][DBLP]
ReCoSoC, 2005, pp:35-42 [Conf]
- Yann Thoma, Eduardo Sanchez
An adaptive FPGA and its distributed routing. [Citation Graph (0, 0)][DBLP]
ReCoSoC, 2005, pp:43-53 [Conf]
- Peter Zipf, Claude Stötzler, Manfred Glesner
Analysis and Architectural Study of a Hybrid ASIC/Configurable State Machine Model. [Citation Graph (0, 0)][DBLP]
ReCoSoC, 2005, pp:53-58 [Conf]
- Hayder Mrabet, Zied Marrakchi, Habib Mehrez, André Tissot
Implementation of Scalable Embedded FPGA for SOC. [Citation Graph (0, 0)][DBLP]
ReCoSoC, 2005, pp:59-62 [Conf]
- Jean-Philippe Diguet, Yvan Eustache, Nader Ben Amor, Soufien Hammami
Feedback control modelling for learning reconfigurable embedded systems. [Citation Graph (0, 0)][DBLP]
ReCoSoC, 2005, pp:63-70 [Conf]
- François Verdier, Jean-Christophe Prévotet, Amine Benkhelifa, Daniel Chillet, Sébastien Pillement
Exploring RTOS issues with a high-level model of a reconfigurable SoC platform. [Citation Graph (0, 0)][DBLP]
ReCoSoC, 2005, pp:71-78 [Conf]
- Leandro Soares Indrusiak, Manfred Glesner
Experiences on Actor-oriented Design of Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
ReCoSoC, 2005, pp:79-84 [Conf]
- Thomas Hollstein, Sujan Pandey, Manfred Glesner
Advanced On-Chip Communication Architectures and Routing Methods for Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
ReCoSoC, 2005, pp:85-92 [Conf]
- Julien Delorme, Dominique Houzet, Romain Lemaire, Didier Lattard
Proposition of a benchmark for evaluation of cores mapping onto NoC architectures. [Citation Graph (0, 0)][DBLP]
ReCoSoC, 2005, pp:93-98 [Conf]
- David A. Sigüenza-Tortosa, Jari Nurmi
System Monitoring and Reconfiguration in Proteo NoC. [Citation Graph (0, 0)][DBLP]
ReCoSoC, 2005, pp:99-104 [Conf]
- Laurent Fesquet, Jerome Quartana, Marc Renaudin
Asynchronous Systems on Programmable Logic. [Citation Graph (0, 0)][DBLP]
ReCoSoC, 2005, pp:105-112 [Conf]
- Nicolas Bruchon, Gaston Cambon, Lionel Torres, Gilles Sassatelli
Non-volatile SRAM-FPGA based on magnetic tunnelling junction. [Citation Graph (0, 0)][DBLP]
ReCoSoC, 2005, pp:113-120 [Conf]
- Ian O'Connor, Matthieu Briere, Emmanuel Drouard, Art Kazmierczak, Faress Tissafi-Drissi, David Navarro, Fabien Mieyeville, Joni Dambre, Dirk Stroobandt, J.-M. Fedeli, Zbigniew Lisik, Frédéric Gaffiot
Towards reconfigurable optical networks on chip. [Citation Graph (0, 0)][DBLP]
ReCoSoC, 2005, pp:121-128 [Conf]
- Pierre Boulet, Arnaud Cuccuru, Jean-Luc Dekeyser, Ashish Meena
Model Driven Engineering for Regular MPSoC Co-design. [Citation Graph (0, 0)][DBLP]
ReCoSoC, 2005, pp:129-136 [Conf]
- Nathalie Julien, Johann Laurent, Eric Senn, David Elléouet, Yannig Savary, Nabil Abdelli, J. Ktari
Power/Energy Estimation in SoCs by Multi-Level Parametric Modeling. [Citation Graph (0, 0)][DBLP]
ReCoSoC, 2005, pp:137-142 [Conf]
- Luís Gomes, João Paulo Barros, Anikó Costa, Rui Pais, Filipe Moutinho
Formal methods for Embedded Systems Co-design: the FORDESIGN project. [Citation Graph (0, 0)][DBLP]
ReCoSoC, 2005, pp:143-150 [Conf]
- Tudor Murgan, Abdulfattah Mohammad Obeid, Andre Guntoro, Peter Zipf, Manfred Glesner, Ulrich Heinkel
Design and Implementation of a Multi-Core Architecture for Overhead Processing in Optical Transport Networks. [Citation Graph (0, 0)][DBLP]
ReCoSoC, 2005, pp:151-156 [Conf]
- Alfredo Rosado Muñoz, Emilio Soria-Olivas, Joan Vila-Francés, Jordi Muñoz-Marí, Javier Calpe-Maravilla
Implementation Challenges in Complex Adaptive Systems. [Citation Graph (0, 0)][DBLP]
ReCoSoC, 2005, pp:157-162 [Conf]
- Nicolas Valette, Lionel Torres, Frédéric Bancel, Nicolas Bérard
Integration of Reconfigurable Logic on Secure Circuits. [Citation Graph (0, 0)][DBLP]
ReCoSoC, 2005, pp:163-168 [Conf]
- Daniel Mesquita, Jean-Denis Techer, Lionel Torres, Gilles Sassatelli, Gaston Cambon, Michel Robert, Fernando Moraes
A new hardware countermeasure for masking power signatures of crypto cores. [Citation Graph (0, 0)][DBLP]
ReCoSoC, 2005, pp:169-176 [Conf]
- AbdelHalim Samahi, Sami Boukhechem, El-Bay Bourennane, Nasser E. Idirene
STARSoC : A C-based platform for rapid prototyping of embedded system. [Citation Graph (0, 0)][DBLP]
ReCoSoC, 2005, pp:177-182 [Conf]
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