Ruby B. Lee Processor Architecture for Trustworthy Computers. [Citation Graph (0, 0)][DBLP] Asia-Pacific Computer Systems Architecture Conference, 2005, pp:1-2 [Conf]
Amjad Mohsen, Richard Hofmann Efficient Voltage Scheduling and Energy-Aware Co-synthesis for Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP] Asia-Pacific Computer Systems Architecture Conference, 2005, pp:3-14 [Conf]
Ming Zhang, Hau T. Ngo, Vijayan K. Asari Design of an Efficient Multiplier-Less Architecture for Multi-dimensional Convolution. [Citation Graph (0, 0)][DBLP] Asia-Pacific Computer Systems Architecture Conference, 2005, pp:65-78 [Conf]
Flavius Gruian, Zoran A. Salcic Designing a Concurrent Hardware Garbage Collector for Small Embedded Systems. [Citation Graph (0, 0)][DBLP] Asia-Pacific Computer Systems Architecture Conference, 2005, pp:281-294 [Conf]
Jesse Fang Challenges and Opportunities on Multi-core Microprocessor. [Citation Graph (0, 0)][DBLP] Asia-Pacific Computer Systems Architecture Conference, 2005, pp:389-390 [Conf]
K. S. Tham, Douglas L. Maskell Software-Oriented System-Level Simulation for Design Space Exploration of Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP] Asia-Pacific Computer Systems Architecture Conference, 2005, pp:391-404 [Conf]
P. C. Kwan, C. T. Clarke FPGAs for Improved Energy Efficiency in Processor Based Systems. [Citation Graph (0, 0)][DBLP] Asia-Pacific Computer Systems Architecture Conference, 2005, pp:440-449 [Conf]
Navid Imani, Hamid Sarbazi-Azad The Star-Pyramid Graph: An Attractive Alternative to the Pyramid. [Citation Graph (0, 0)][DBLP] Asia-Pacific Computer Systems Architecture Conference, 2005, pp:509-519 [Conf]
S. Suresh, V. Mani, S. N. Omkar, H. J. Kim A Real Coded Genetic Algorithm for Data Partitioning and Scheduling in Networks with Arbitrary Processor Release Time. [Citation Graph (0, 0)][DBLP] Asia-Pacific Computer Systems Architecture Conference, 2005, pp:529-539 [Conf]
Zhen Liu, Jiaoying Shi, Haoyu Peng, Hua Xiong D3DPR: A Direct3D-Based Large-Scale Display Parallel Rendering System Architecture for Clusters. [Citation Graph (0, 0)][DBLP] Asia-Pacific Computer Systems Architecture Conference, 2005, pp:540-550 [Conf]
Jongmyon Kim, D. Scott Wills, Linda M. Wills Determining Optimal Grain Size for Efficient Vector Processing on SIMD Image Processing Architectures. [Citation Graph (0, 0)][DBLP] Asia-Pacific Computer Systems Architecture Conference, 2005, pp:551-565 [Conf]
Kyong Jung, Chanik Park A Technique to Reduce Preemption Overhead in Real-Time Multiprocessor Task Scheduling. [Citation Graph (0, 0)][DBLP] Asia-Pacific Computer Systems Architecture Conference, 2005, pp:566-579 [Conf]
DongSup Song, Sungho Kang Increasing Embedding Probabilities of RPRPs in RIN Based BIST. [Citation Graph (0, 0)][DBLP] Asia-Pacific Computer Systems Architecture Conference, 2005, pp:600-613 [Conf]
Jin-Ho Ahn, Byung In Moon, Sungho Kang A Practical Test Scheduling Using Network-Based TAM in Network on Chip Architecture. [Citation Graph (0, 0)][DBLP] Asia-Pacific Computer Systems Architecture Conference, 2005, pp:614-624 [Conf]
T. S. B. Sudarshan, Rahil Mir, S. Vijayalakshmi DRIL- A Flexible Architecture for Blowfish Encryption Using Dynamic Reconfiguration, Replication, Inner-Loop Pipelining, Loop Folding Techniques. [Citation Graph (0, 0)][DBLP] Asia-Pacific Computer Systems Architecture Conference, 2005, pp:625-639 [Conf]
Khaled Z. Ibrahim Efficient Architectural Support for Secure Bus-Based Shared Memory Multiprocessor. [Citation Graph (0, 0)][DBLP] Asia-Pacific Computer Systems Architecture Conference, 2005, pp:640-654 [Conf]
Dan Mossop, Ronald Pose Covert Channel Analysis of the Password-Capability System. [Citation Graph (0, 0)][DBLP] Asia-Pacific Computer Systems Architecture Conference, 2005, pp:655-668 [Conf]
Jong-Sun Kim, Ji-Yoon Yoo Application of Real-Time Object-Oriented Modeling Technique for Real-Time Computer Control. [Citation Graph (0, 0)][DBLP] Asia-Pacific Computer Systems Architecture Conference, 2005, pp:680-692 [Conf]
Ravi Kumar Satzoda, Chip-Hong Chang VLSI Performance Evaluation and Analysis of Systolic and Semisystolic Finite Field Multipliers. [Citation Graph (0, 0)][DBLP] Asia-Pacific Computer Systems Architecture Conference, 2005, pp:693-706 [Conf]
Sun-Kuk Noh A Study on the Performance Evaluation of Forward Link in CDMA Mobile Communication Systems. [Citation Graph (0, 0)][DBLP] Asia-Pacific Computer Systems Architecture Conference, 2005, pp:728-735 [Conf]
Weng-Fai Wong Targeted Data Prefetching. [Citation Graph (0, 0)][DBLP] Asia-Pacific Computer Systems Architecture Conference, 2005, pp:775-786 [Conf]
Pramod Kumar Meher Area-Time Efficient Systolic Architecture for the DCT. [Citation Graph (0, 0)][DBLP] Asia-Pacific Computer Systems Architecture Conference, 2005, pp:787-794 [Conf]
Gab Jung, Seong Park, Jung Kim Efficient VLSI Architectures for Convolution and Lifting Based 2-D Discrete Wavelet Transform. [Citation Graph (0, 0)][DBLP] Asia-Pacific Computer Systems Architecture Conference, 2005, pp:795-804 [Conf]
Himanshu Thapliyal, M. B. Srinivas A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures. [Citation Graph (0, 0)][DBLP] Asia-Pacific Computer Systems Architecture Conference, 2005, pp:805-817 [Conf]
In-Su Yoon, Sang-Hwa Chung Implementation and Analysis of TCP/IP Offload Engine and RDMA Transfer Mechanisms on an Embedded System. [Citation Graph (0, 0)][DBLP] Asia-Pacific Computer Systems Architecture Conference, 2005, pp:818-830 [Conf]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
