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Conferences in DBLP

IEEE International Workshop on Rapid System Prototyping (rsp)
2000 (conf/rsp/2000)

  1. Marios Iliopoulos, Theodore Antonakopoulos
    A Methodology for Implementing Medium Access Protocols Using a General Parameterized Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:2-7 [Conf]
  2. Amer Baghdadi, Nacer-Eddine Zergainoh, Wander O. Cesário, T. Roudier, Ahmed Amine Jerraya
    Design Space Exploration for Hardware/Software Codesign of Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:8-13 [Conf]
  3. Johan Cockx
    Efficient Modeling of Preemption in a Virtual Prototype. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:14-19 [Conf]
  4. Randall S. Janka, Linda M. Wills
    Combining Virtual Benchmarking with Rapid System Prototyping for Real-Time Embedded Multiprocessor Signal Processing System Codesign. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:20-0 [Conf]
  5. Juan Carlos Nogueira, Luqi, Swapan Bhattacharya
    A Risk Assessment Model for Software Prototyping Projects. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:28-33 [Conf]
  6. Rajat Moona
    Processor Models for Retargetable Tools. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:34-39 [Conf]
  7. Yolanda González Arechavala, Fernando de Cuadra García
    MODUS: Integrated Behavior-Oriented Model for Rapid Prototyping. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:40-45 [Conf]
  8. Myung-Hwan Park, Ki-Seok Bang, Jin-Young Choi, Inhye Kang
    Equivalence Checking of Two Statechart Specifications. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:46-51 [Conf]
  9. Martin Dimmler, Yves Piguet
    Intuitive Design of Complex Real-Time Control Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:52-0 [Conf]
  10. Lovic Gauthier, Ahmed Amine Jerraya
    Cycle-True Simulation of the ST10 Microcontroller Including the Core and the Peripherals. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:60-65 [Conf]
  11. Kenneth B. Kent, Micaela Serra
    Hardware/Software Co-Design of a Java Virtual Machine. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:66-71 [Conf]
  12. Kyung-soo Oh, Sang-yong Yoon, Soo-Ik Chae
    Emulator Environment Based on an FPGA Prototyping Board. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:72-77 [Conf]
  13. Andreas Koch
    A Comprehensive Prototyping-Platform for Hardware-Software Codesign. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:78-0 [Conf]
  14. Bishnupriya Bhattacharya, Shuvra S. Bhattacharyya
    Quasi-Static Scheduling of Reconfigurable Dataflow Graphs for DSP Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:84-89 [Conf]
  15. P. Poure, F. Aubépart, F. Braun
    A Design Methodology for Hardware Prototyping of Integrated AC Drive Control: Application to Direct Torque Control of an Induction Machine. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:90-0 [Conf]
  16. N. Cañellas, J. M. Moreno
    Speeding up Hardware Prototyping by Incremental Simulation/Emulation. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:98-102 [Conf]
  17. V. K. Jain
    Mapping a High-Speed Wireless Communication Function to the Reconfigurable J-Platform. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:103-108 [Conf]
  18. Dirk Eilers, Alfred Voglgsang, Arnold Plankl, Gerri Körner, Helmut Steckenbiller, Rudi Knorr
    A Prototype of an AAL for High Bit Rate Real-Time Data Transmission System over ATM Networks Using a RSE CODEC. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:109-114 [Conf]
  19. Wolfram Hardt, Bernd Kleinjohann, Achim Rettberg
    The FLYSIG Prototyping Approach. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:115-0 [Conf]
  20. David J. Greaves
    A Verilog to C Compiler. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:122-127 [Conf]
  21. Dan Marius Regep, Fabrice Kordon
    Using MetaScribe to Prototype an UML to C++/Ada95 Code Generator. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:128-133 [Conf]
  22. Annette Muth, Thomas Kolloch, Thomas Maier-Komor, Georg Färber
    An Evaluation of Code Generation Strategies Targeting Hardware for the Rapid Prototyping of SDL-Specifications. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:134-0 [Conf]
  23. Ansgar Bredenfeld
    Integration and Evolution of Model-Based Tool Prototypes. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:142-147 [Conf]
  24. Romain Kamdem, Alain Fonkoua
    Coprocessor Synthesis of Multirate System Using Static Scheduling Theory. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:148-153 [Conf]
  25. Frank-Michael Renner, Jürgen Becker, Manfred Glesner
    Automated Communication Synthesis for Architecture-Precise Rapid Prototyping of Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:154-159 [Conf]
  26. Jürgen Becker, Lukusa D. Kabulepa, Frank-Michael Renner, Manfred Glesner
    Simulation and Rapid Prototyping of Flexible Systems-on-a-Chip for Future Mobile Communication Applications. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:160-0 [Conf]
  27. Francisco Barat, Rudy Lauwereins
    Reconfigurable Instruction Set Processors: A Survey. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:168-173 [Conf]
  28. Eduardo de la Torre, Teresa Riesgo, J. Uceda, E. Macip, M. Rizzi
    Highly Configurable Control Boards: A Tool and a Design Experience. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:174-0 [Conf]
  29. Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu
    Power-Constrained Block-Test List Scheduling. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:182-187 [Conf]
  30. Juan de Vicente, Juan Lanchares, Román Hermida
    Adaptive FPGA Placement by Natural Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:188-193 [Conf]
  31. Yajun Ha, Patrick Schaumont, Marc Engels, Serge Vernalde, Freddy Potargent, Luc Rijnders, Hugo De Man
    A Hardware Virtual Machine for the Networked Reconfiguration. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:194-199 [Conf]
  32. Helena Krupnova, Gabriele Saucier
    FPGA Technology Snapshot: Current Devices and Design Tools. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:200-0 [Conf]
  33. P. G. Prasad
    Validation of Link Layer Synthesizable Core - A Prototyping Case Study. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:208-213 [Conf]
  34. Ulrich Mayer, Manfred Glesner
    Hardware Accelerated Estimation of Multiplexer-Introduced Loss for MPEG-4 Data Streams. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:214-0 [Conf]
  35. Göran Eggers, Hans Christoph Zeidler
    Efficient Clock-Cycle Precise Simulation at Architecture Level in C++. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:222-0 [Conf]
  36. Carsten Nitsch, Karlheinz Weiß, Thorsten Steckstor, Wolfgang Rosenstiel
    Embedded System Architecture Design Based on Real-Time Emulation. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2000, pp:228-233 [Conf]
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