Conferences in DBLP
Morteza Saheb Zamani , Graham R. Hellestrand A neural network approach to the placement problem. [Citation Graph (0, 0)][DBLP ] Conf ] Gyeong Lyong Park , Kyung Hi Chang , Jae Seok Kim , Kyung Soo Kim System-level verification of CDMA modem ASIC. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Tai Yan Region definition and ordering assignment with the minimization of the number of switchboxes. [Citation Graph (0, 0)][DBLP ] Conf ] Bernhard M. Riess , Heiko A. Giselbrecht , Bernd Wurth A new K-way partitioning approach for multiple types of FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Keisuke Okada , Shun Morikawa , Isao Shirakawa , Sumitaka Takeuchi A design of high-performance multiplier for digital video transmission. [Citation Graph (0, 0)][DBLP ] Conf ] José M. Quintana , Maria J. Avedillo , Maria P. Parra , José L. Huertas Optimum PLA folding through boolean satisfiability. [Citation Graph (0, 0)][DBLP ] Conf ] Yu-Liang Wu , Malgorzata Marek-Sadowska Routing on regular segmented 2-D FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Miodrag Potkonjak , Sujit Dey , Rabindra K. Roy Synthesis-for-testability using transformations. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Miyashita Extending pitchmaking algorithms to layouts with multiple grid constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Mikako Miyama , Goichi Yokomizo , Masato Iwabuchi , Masami Kinoshita An efficient logic/circuit mixed-mode simulator for analysis of power supply voltage fluctutation. [Citation Graph (0, 0)][DBLP ] Conf ] Akira Nagao , Chiyoshi Yoshioka , Takashi Kambe , Isao Shirakawa A layout approach to Monolithic Microwave IC. [Citation Graph (0, 0)][DBLP ] Conf ] Mahesh Mehendale , Sunil D. Sherlekar , G. Venkatesh Techniques for low power realization for FIR filters. [Citation Graph (0, 0)][DBLP ] Conf ] Atsushi Masuda , Hiroshi Imai , Jeffery P. Hansen , Masatoshi Sekine Search space reduction in high level synthesis by use of an initial circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Akira Motohara , Sadami Takeoka , Toshinori Hosokawa , Mitsuyasu Ohta , Yuji Takai , Michihiro Matsumoto , Michiaki Muraoka Design for testability using register-transfer level partial scan selection. [Citation Graph (0, 0)][DBLP ] Conf ] Vasily G. Moshnyaga , Fumiaki Ohbayashi , Keikichi Tamaru A scheduling algorithm for synthesis of bus-partitioned architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Janett Mohnke , Paul Molitor , Sharad Malik Limits of using signatures for permutation independent Boolean comparison. [Citation Graph (0, 0)][DBLP ] Conf ] Per Lindgren Improved computational methods and lazy evaluation of the Ordered Ternary Decision Diagram. [Citation Graph (0, 0)][DBLP ] Conf ] How-Rern Lin , TingTing Hwang Power recduction by gate sizing with path-oriented slack calculation. [Citation Graph (0, 0)][DBLP ] Conf ] Sadiq M. Sait , Habib Youssef , Shahid K. Tanvir , Muhammad S. T. Benten Timing influenced generell-cell genetic floorplanner. [Citation Graph (0, 0)][DBLP ] Conf ] Radomir S. Stankovic Some remarks about spectral transform interpretation of MTBDDs and EVBDDs. [Citation Graph (0, 0)][DBLP ] Conf ] Christoph Scholl , Paul Molitor Communication based FPGA synthesis for multi-output Boolean functions. [Citation Graph (0, 0)][DBLP ] Conf ] Hitoshi Yoshizawa How sub-micron delay and timing issues will be solved? [Citation Graph (0, 0)][DBLP ] Conf ] Jeongsik Yang , Chanhong Park , Beomsup Kim A digital audio signal processor for cellular phone application. [Citation Graph (0, 0)][DBLP ] Conf ] Shigeru Yamashita , Yahiko Kambayashi , Saburo Muroga Optimization methods for lookup-table-based FPGAs using transduction method. [Citation Graph (0, 0)][DBLP ] Conf ] Richard K. Wallace Design automation 2000 (panel session): challenges for gigabit-era. [Citation Graph (0, 0)][DBLP ] Conf ] Kazuyuki Wada , Shigetaka Takagi , Zdzislaw Czarnul , Nobuo Fujii Design automation for integrated continuous-time filters using integrators. [Citation Graph (0, 0)][DBLP ] Conf ] Eugenio Villar , Masaharu Imai Future direction of synthesizabilty and interoperability of HDL's: part 2. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Uno , Toru Chiba , Keiji Kumatani , Isao Shirakawa Synthesis and simulation of digital demodulator for infrared data communication. [Citation Graph (0, 0)][DBLP ] Conf ] J. P. Tual , M. Thill , C. Bernard , Huy Nam Nguyen , F. Mottini , M. Moreau , P. Vallet Auriga2: a 4.7 million-transistor CISC microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Masahiro Tsuchiya , Tetsushi Koide , Shin'ichi Wakabayashi , Noriyoshi Yoshida A three-layer over-cell multi-channel routing method for a new cell model. [Citation Graph (0, 0)][DBLP ] Conf ] Chia-Chun Tsai , De-Yu Kao , Chung-Kuan Cheng , Ting-Ting Y. Lin Performance driven multiple-source bus synthesis using buffer insertion. [Citation Graph (0, 0)][DBLP ] Conf ] Nozomu Togawa , Masao Sato , Tatsuo Ohtsuki Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm FPGAs with performance optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Vivek Tiwari , Mike Tien-Chien Lee Power analysis of a 32-bit embedded microcontroller. [Citation Graph (0, 0)][DBLP ] Conf ] Man-Fai Yu , Wayne Wei-Ming Dai Pin assignment and routing on a single-layer Pin Grid Array. [Citation Graph (0, 0)][DBLP ] Conf ] Katsunori Tani A robust min-cut improvement algorithm based on dynamic look-ahead weighting. [Citation Graph (0, 0)][DBLP ] Conf ] C.-J. Shi , Janusz A. Brzozowski A framework for the analysis and design of algorithms for a class of VLSI-CAD optimization problems. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Zen Shen , Jing-Yuan Lin , Fong-Wen Wang Transistor reordering rules for power reduction in CMOS gates. [Citation Graph (0, 0)][DBLP ] Conf ] Kinya Tabuchi Electronic data book: current status of standard representation and future perspective. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Chang Lin , David Ihsin Cheng , Malgorzata Marek-Sadowska , Kuang-Chien Chen Logic rectification and synthesis for engineering change. [Citation Graph (0, 0)][DBLP ] Conf ] J. Y. Lim , G. Kim , I.-S. O , J. H. Cho , Y. Kim , H. Y. Kim A CSIC implementation with POCSAG decoder and microcontroller for paging applications. [Citation Graph (0, 0)][DBLP ] Conf ] Jung-Yong Lee , Eugene Shragowitz Technology mapping for FPGAs with complex block architectures by fuzzy logic techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Uwe Gläser , Kwang-Ting Cheng Logic optimization by an improved sequential redundancy addition and removal techniques. [Citation Graph (0, 0)][DBLP ] Conf ] A. Ghosh , M. Bershteyn , R. Casley , C. Chien , A. Jain , M. Lipsie , D. Tarrodaychik , O. Yamamo A hardware-software co-simulator for embedded system design and debugging. [Citation Graph (0, 0)][DBLP ] Conf ] Masahiro Fukui , Noriko Shinomiya , Toshiro Akino A new layout synthesis for leaf cell design. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Jong Fang , Allen C.-H. Wu , Tsing-Gen Lee EMPAR: an interactive synthesis environment for hardware emulations. [Citation Graph (0, 0)][DBLP ] Conf ] Marco A. Escalante , Nikitas J. Dimopoulos Assessing the feasibility of interface designs before their implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Rolf Drechsler , Bernd Becker Learning heuristics by genetic algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjay Dhar , Dave J. Gurney Current and charge estimation in CMOS circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Denis Deschacht , Christophe Dabrin A new and accurate interconnection delay time evaluation in a general tree-type network. [Citation Graph (0, 0)][DBLP ] Conf ] Debatosh Debnath , Tsutomu Sasao GRMIN: a heuristic simplification algorithm for generalized Reed-Muller expressions. [Citation Graph (0, 0)][DBLP ] Conf ] T. Raju Damarla , Wei Su , Gerald T. Michael , Moon J. Chung , Charles E. Stroud A built-in self test scheme for VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Dongmin Xu Exploitation signal flow and logic dependency in standard cell placement. [Citation Graph (0, 0)][DBLP ] Conf ] Nguyen-Ngoc Bình , Masaharu Imai , Akichika Shiomi , Nobuyuki Hikichi A hardware/software codesign method for pipelined instruction set processor using adaptive database. [Citation Graph (0, 0)][DBLP ] Conf ] Ivanil S. Bonatti , Renato J. O. Figueiredo Stoht: an SDL-to-hardware translator. [Citation Graph (0, 0)][DBLP ] Conf ] T. Bogue , Helmut Jürgensen , Michael Gössel BIST with negligible aliasing through random cover circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Chun-Te Chen , Liang-Gee Chen , Jue-Hsuan Hsiao A hardware-oriented design for weighted median filters. [Citation Graph (0, 0)][DBLP ] Conf ] Chip-Hong Chang , Bogdan J. Falkowski Flexible optimization of fixed polarity Reed-Muller expansions for multiple and output completely and incompletely specified boolean functions. [Citation Graph (0, 0)][DBLP ] Conf ] Takashi Aoki , Tomoji Toriyama , Kenji Ishikawa , Kennosuke Fukami A tool for measuring quality of test pattern for LSIs' functional design. [Citation Graph (0, 0)][DBLP ] Conf ] Reiner W. Hartenstein , Rainer Kress A datapath synthesis system for the reconfigurable datapath architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Marc J. M. Heijligers , L. J. M. Cluitmans , Jochen A. G. Jess High-level synthesis scheduling and allocation using genetic algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroyuki Higuchi , Yusuke Matsunaga Implicit prime compatible generation for minimizing incompletely specified finite state machines. [Citation Graph (0, 0)][DBLP ] Conf ] Jong Tae Lee , Jaemin Kim , Jae Cheol Son Architectural simulation for a programmable DSP chip set. [Citation Graph (0, 0)][DBLP ] Conf ] Hae-Dong Lee , Sun-Young Hwang A scheduling algorithm for multiport memory minimization in datapath synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroaki Kunieda , Yusong Liao , Dongju Li , Kazuhito Ito Automatic design for bit-serial MSPA architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Alex Kondratyev , Michael Kishinevsky , Alexandre Yakovlev On hazard-free implementation of speed-independent circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Masaki Kondo , Hidetoshi Onodera , Keikichi Tamaru A model-adaptable MOSFET parameter extraction system. [Citation Graph (0, 0)][DBLP ] Conf ] Tetsushi Koide , Mitsuhiro Ono , Shin'ichi Wakabayashi , Yutaka Nishimaru A new performance driven placement method with the Elmore delay model for row based VLSIs. [Citation Graph (0, 0)][DBLP ] Conf ] Noriya Kobayashi , Sharad Malik Delay abstraction in combinational logic circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Chunghee Kim , Hyunchul Shin , Young-Uk Yu Performance-driven circuit partitioning for prototyping by using multiple FPGA chips. [Citation Graph (0, 0)][DBLP ] Conf ] Yongjoo Kim , Kyuseok Kim , Youngsoo Shin , Taekyoon Ahn , Wonyong Sung , Kiyoung Choi , Soonhoi Ha An integrated hardware-software cosimulation environment for heterogeneous systems prototyping. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshinori Katsura , Tetsushi Koide , Shin'ichi Wakabayashi , Noriyoshi Yoshida A new system partitioning method under performance and physical constraints for multi-chip modules. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Q. Kang , Eugene Shragowitz Generic fuzzy logic CAD development tool. [Citation Graph (0, 0)][DBLP ] Conf ] Hilary J. Kahn EDIF version 350/400 and information modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Pradip K. Jha , Nikil D. Dutt , Sri Parameswaran Reclocking for high-level synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Won-Young Jung , Ghun-Up Cha , Young-Bae Kim , Jun-Ho Baek , Choon-Kyung Kim Integrated interconnect circuit modeling for VLSI design. [Citation Graph (0, 0)][DBLP ] Conf ] Shinya Ishihara , Shin-ichi Minato Manipulation of regular expressions under length constraints using zero-suppressed-BDDs. [Citation Graph (0, 0)][DBLP ] Conf ] Masaharu Imai , Eugenio Villar Future direction of synthesizability and interoperability of HDL's: part 1. [Citation Graph (0, 0)][DBLP ] Conf ] Shih-Hsu Huang , Ta-Yung Liu , Yu-Chin Hsu , Yen-Jen Oyang Synthesis of false loop free circuits. [Citation Graph (0, 0)][DBLP ] Conf ] T. Aoki , Masami Murakata , Takashi Mitsuhashi , Nobuyuki Goto Fanout-tree restructuring algorithm for post-placement timing optimization. [Citation Graph (0, 0)][DBLP ] Conf ] 